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LA-MachXO Automotive Family Data Sheet
DS1003 Version 01.5, November 2007
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LA-MachXO Automotive Family Data Sheet Introduction
Data Sheet DS1003
April 2006
Features
Non-volatile, Infinitely Reconfigurable
* Instant-on - powers up in microseconds * Single chip, no external configuration memory required * Excellent design security, no bit stream to intercept * Reconfigure SRAM based logic in milliseconds * SRAM and non-volatile memory programmable through JTAG port * Supports background programming of non-volatile memory
* Programmable sysIOTM buffer supports wide range of interfaces: - LVCMOS 3.3/2.5/1.8/1.5/1.2 - LVTTL - PCI - LVDS, Bus-LVDS, LVPECL, RSDS
sysCLOCKTM PLLs
* Up to two analog PLLs per device * Clock multiply, divide, and phase shifting
System Level Support
* IEEE Standard 1149.1 Boundary Scan * Onboard oscillator * Devices operate with 3.3V, 2.5V, 1.8V or 1.2V power supply * IEEE 1532 compliant in-system programming
AEC-Q100 Tested and Qualified Sleep Mode
* Allows up to 100x static current reduction
TransFRTM Reconfiguration (TFR)
* In-field logic update while system operates
Introduction
The LA-MachXO automotive device family is optimized to meet the requirements of applications traditionally addressed by CPLDs and low capacity FPGAs: glue logic, bus bridging, bus interfacing, power-up control, and control logic. These devices bring together the best features of CPLD and FPGA devices on a single chip in AEC-Q100 tested and qualified versions. The devices use look-up tables (LUTs) and embedded block memories traditionally associated with FPGAs for flexible and efficient logic implementation. Through nonvolatile technology, the devices provide the single-chip,
High I/O to Logic Density
* * * * 256 to 2280 LUT4s 73 to 271 I/Os with extensive package options Density migration supported Lead free/RoHS compliant packaging
Embedded and Distributed Memory
* Up to 27.6 Kbits sysMEMTM Embedded Block RAM * Up to 7.5 Kbits distributed RAM * Dedicated FIFO control logic
Flexible I/O Buffer
Table 1-1. LA-MachXO Automotive Family Selection Guide
Device LUTs Dist. RAM (Kbits) EBR SRAM (Kbits) Number of EBR SRAM Blocks (9 Kbits) VCC Voltage Number of PLLs Max. I/O Packages 100-pin Lead-Free TQFP (14x14 mm) 144-pin Lead-Free TQFP (20x20 mm) 256-ball Lead-Free ftBGA (17x17 mm) 324-ball Lead-Free ftBGA (19x19 mm) 78 74 113 159 73 113 211 73 113 211 271 LAMXO256E/C 256 2.0 0 0 1.2/1.8/2.5/3.3V 0 78 LAMXO640E/C 640 6.0 0 0 1.2/1.8/2.5/3.3V 0 159 LAMXO1200E 1200 6.25 9.2 1 1.2 1 211 LAMXO2280E 2280 7.5 27.6 3 1.2 2 271
(c) 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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DS1003 Introduction_01.0
Lattice Semiconductor
Introduction LA-MachXO Automotive Family Data Sheet
high-security, instant-on capabilities traditionally associated with CPLDs. Finally, advanced process technology and www..com careful design will provide the high pin-to-pin performance also associated with CPLDs. The ispLEVER(R) design tools from Lattice allow complex designs to be efficiently implemented using the LAMachXO automotive family of devices. Popular logic synthesis tools provide synthesis library support for LAMachXO. The ispLEVER tools use the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the LA-MachXO device. The ispLEVER tool extracts the timing from the routing and back-annotates it into the design for timing verification.
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LA-MachXO Automotive Family Data Sheet Architecture
Data Sheet DS1003
February 2007
Architecture Overview
The LA-MachXO family architecture contains an array of logic blocks surrounded by Programmable I/O (PIO). Some devices in this family have sysCLOCK PLLs and blocks of sysMEMTM Embedded Block RAM (EBRs). Figures 2-1, 2-2, and 2-3 show the block diagrams of the various family members. The logic blocks are arranged in a two-dimensional grid with rows and columns. The EBR blocks are arranged in a column to the left of the logic array. The PIO cells are located at the periphery of the device, arranged into Banks. The PIOs utilize a flexible I/O buffer referred to as a sysIO interface that supports operation with a variety of interface standards. The blocks are connected with many vertical and horizontal routing channel resources. The place and route software tool automatically allocates these routing resources. There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and the Programmable Functional unit without RAM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM, and register functions. The PFF block contains building blocks for logic, arithmetic, ROM, and register functions. Both the PFU and PFF blocks are optimized for flexibility, allowing complex designs to be implemented quickly and effectively. Logic blocks are arranged in a two-dimensional array. Only one type of block is used per row. In the LA-MachXO family, the number of sysIO Banks varies by device. There are different types of I/O Buffers on different Banks. See the details in later sections of this document. The sysMEM EBRs are large, dedicated fast memory blocks; these blocks are found only in the larger devices. These blocks can be configured as RAM, ROM or FIFO. FIFO support includes dedicated FIFO pointer and flag "hard" control logic to minimize LUT use. The LA-MachXO architecture provides up to two sysCLOCKTM Phase Locked Loop (PLL) blocks on larger devices. These blocks are located at either end of the memory blocks. The PLLs have multiply, divide, and phase shifting capabilities that are used to manage the frequency and phase relationships of the clocks. Every device in the family has a JTAG Port that supports programming and configuration of the device as well as access to the user logic. The LA-MachXO devices are available for operation from 3.3V, 2.5V, 1.8V, and 1.2V power supplies, providing easy integration into the overall system.
(c) 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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DS1003 Architecture_01.2
Lattice Semiconductor
Figure 2-1. Top View of the LA-MachXO1200 Device1 www..com
Architecture LA-MachXO Automotive Family Data Sheet
PIOs Arranged into sysIO Banks
sysMEM Embedded Block RAM (EBR)
Programmable Functional Units with RAM (PFUs)
Programmable Functional Units without RAM (PFFs)
sysCLOCK PLL JTAG Port 1. Top view of the LA-MachXO2280 device is similar but with higher LUT count, two PLLs, and three EBR blocks.
Figure 2-2. Top View of the LA-MachXO640 Device
PIOs Arranged into sysIO Banks
Programmable Function Units without RAM (PFFs)
Programmable Function Units with RAM (PFUs)
JTAG Port
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Figure 2-3. Top View of the LA-MachXO256 Device www..com
Architecture LA-MachXO Automotive Family Data Sheet
JTAG Port
Programmable Function Units without RAM (PFFs)
PIOs Arranged into sysIO Banks
Programmable Function Units with RAM (PFUs)
PFU Blocks
The core of the LA-MachXO devices consists of PFU and PFF blocks. The PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM, and Distributed ROM functions. PFF blocks can be programmed to perform Logic, Arithmetic, and Distributed ROM functions. Except where necessary, the remainder of this data sheet will use the term PFU to refer to both PFU and PFF blocks. Each PFU block consists of four interconnected Slices, numbered 0-3 as shown in Figure 2-4. There are 53 inputs and 25 outputs associated with each PFU block. Figure 2-4. PFU Diagram
From Routing
FCIN
LUT4 & CARRY
LUT4 & CARRY
LUT4 & CARRY
LUT4 & CARRY
LUT4 & CARRY
LUT4 & CARRY
LUT4 & CARRY
LUT4 & CARRY
FCO
Slice 0
Slice 1
Slice 2
Slice 3
D FF/ Latch
D FF/ Latch
D FF/ Latch
D FF/ Latch
D FF/ Latch
D FF/ Latch
D FF/ Latch
D FF/ Latch
To Routing
Slice
Each Slice contains two LUT4 lookup tables feeding two registers (programmed to be in FF or Latch mode), and some associated logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7, and LUT8. There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock select, chip-select, and wider RAM/ROM functions. Figure 2-5 shows an overview of the internal logic of the Slice. The registers in the Slice can be configured for positive/negative and edge/level clocks.
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Architecture LA-MachXO Automotive Family Data Sheet
There are 14 input signals: 13 signals from routing and one from the carry-chain (from the adjacent Slice/PFU). www..com There are 7 outputs: 6 to the routing and one to the carry-chain (to the adjacent Slice/PFU). Table 2-1 lists the signals associated with each Slice. Figure 2-5. Slice Diagram
To Adjacent Slice/PFU
Slice
OFX1 A1 B1 C1 D1
CO
F1
F SUM D
LUT4 & CARRY
CI
FF/ Latch
Fast Connection to I/O Cell* Q1 To Routing
From Routing
M1 M0
LUT Expansion Mux
A0
B0
CO
OFX0 Fast Connection to I/O Cell* F0
C0 D0
LUT4 & CARRY
CI
F SUM OFX0 D
FF/ Latch
Q0
Control Signals selected and inverted per Slice in routing
CE CLK LSR
From Adjacent Slice/PFU Notes: Some inter-Slice signals are not shown. * Only PFUs at the edges have fast connections to the I/O cell.
Table 2-1. Slice Signal Descriptions
Function Input Input Input Input Input Input Input Output Output Output Output Output Type Data signal Data signal Multi-purpose Control signal Control signal Control signal Inter-PFU signal Data signals Data signals Data signals Data signals Inter-PFU signal Signal Names A0, B0, C0, D0 Inputs to LUT4 A1, B1, C1, D1 Inputs to LUT4 M0/M1 CE LSR CLK FCIN F0, F1 Q0, Q1 OFX0 OFX1 FCO Multipurpose Input Clock Enable Local Set/Reset System Clock Fast Carry In1 LUT4 output register bypass signals Register Outputs Output of a LUT5 MUX Output of a LUT6, LUT7, LUT82 MUX depending on the Slice Fast Carry Out1 Description
1. See Figure 2-4 for connection details. 2. Requires two PFUs.
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Architecture LA-MachXO Automotive Family Data Sheet
Modes of Operation www..com Each Slice is capable of four modes of operation: Logic, Ripple, RAM, and ROM. The Slice in the PFF is capable of all modes except RAM. Table 2-2 lists the modes and the capability of the Slice blocks. Table 2-2. Slice Modes
Logic PFU Slice PFF Slice LUT 4x2 or LUT 5x1 LUT 4x2 or LUT 5x1 Ripple 2-bit Arithmetic Unit 2-bit Arithmetic Unit RAM SP 16x2 N/A ROM ROM 16x1 x 2 ROM 16x1 x 2
Logic Mode: In this mode, the LUTs in each Slice are configured as 4-input combinatorial lookup tables (LUT4). A LUT4 can have 16 possible input combinations. Any logic function with four inputs can be generated by programming this lookup table. Since there are two LUT4s per Slice, a LUT5 can be constructed within one Slice. Larger lookup tables such as LUT6, LUT7, and LUT8 can be constructed by concatenating other Slices. Ripple Mode: Ripple mode allows the efficient implementation of small arithmetic functions. In ripple mode, the following functions can be implemented by each Slice: * * * * * * * Addition 2-bit Subtraction 2-bit Add/Subtract 2-bit using dynamic control Up counter 2-bit Down counter 2-bit Ripple mode multiplier building block Comparator functions of A and B inputs - A greater-than-or-equal-to B - A not-equal-to B - A less-than-or-equal-to B
Two additional signals, Carry Generate and Carry Propagate, are generated per Slice in this mode, allowing fast arithmetic functions to be constructed by concatenating Slices. RAM Mode: In this mode, distributed RAM can be constructed using each LUT block as a 16x2-bit memory. Through the combination of LUTs and Slices, a variety of different memories can be constructed. The ispLEVER design tool supports the creation of a variety of different size memories. Where appropriate, the software will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3 shows the number of Slices required to implement different distributed RAM primitives. Figure 2-6 shows the distributed memory primitive block diagrams. Dual port memories involve the pairing of two Slices. One Slice functions as the read-write port, while the other companion Slice supports the read-only port. For more information on RAM mode in LA-MachXO devices, please see details of additional technical documentation at the end of this data sheet. Table 2-3. Number of Slices Required For Implementing Distributed RAM
SPR16x2 Number of Slices 1 DPR16x2 2
Note: SPR = Single Port RAM, DPR = Dual Port RAM
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Figure 2-6. Distributed Memory Primitives www..com
SPR16x2
AD0 AD1 AD2 AD3 DI0 DI1 WRE CK
Architecture LA-MachXO Automotive Family Data Sheet
DPR16x2
DO0 DO1
WAD0 WAD1 WAD2 WAD3 DI0 DI1 WCK WRE
RAD0 RAD1 RAD2 RAD3 RDO0 RDO1 WDO0 WDO1
ROM16x1
AD0 AD1 AD2 AD3
DO0
ROM Mode: The ROM mode uses the same principal as the RAM modes, but without the Write port. Pre-loading is accomplished through the programming interface during configuration. PFU Modes of Operation Slices can be combined within a PFU to form larger functions. Table 2-4 tabulates these modes and documents the functionality possible at the PFU level. Table 2-4. PFU Modes of Operation
Logic LUT 4x8 or MUX 2x1 x 8 LUT 5x4 or MUX 4x1 x 4 LUT 6x 2 or MUX 8x1 x 2 LUT 7x1 or MUX 16x1 x 1 Ripple 2-bit Add x 4 2-bit Sub x 4 2-bit Counter x 4 2-bit Comp x 4 RAM SPR16x2 x 4 DPR16x2 x 2 SPR16x4 x 2 DPR16x4 x 1 SPR16x8 x 1 ROM ROM16x1 x 8 ROM16x2 x 4 ROM16x4 x 2 ROM16x8 x 1
Routing
There are many resources provided in the LA-MachXO devices to route signals individually or as buses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments. The inter-PFU connections are made with three different types of routing resources: x1 (spans two PFUs), x2 (spans three PFUs) and x6 (spans seven PFUs). The x1, x2, and x6 connections provide fast and efficient connections in the horizontal and vertical directions.
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Architecture LA-MachXO Automotive Family Data Sheet
The ispLEVER design tool takes the output of the synthesis tool and places and routes the design. Generally, the www..com place and route tool is completely automatic, although an interactive routing editor is available to optimize the design.
Clock/Control Distribution Network
The LA-MachXO automotive family of devices provides global signals that are available to all PFUs. These signals consist of four primary clocks and four secondary clocks. Primary clock signals are generated from four 16:1 muxes as shown in Figure 2-7 and Figure 2-8. The available clock sources for the LA-MachXO256 and LA-MachXO640 devices are four dual function clock pins and 12 internal routing signals. The available clock sources for the LAMachXO1200 and LA-MachXO2280 devices are four dual function clock pins, up to nine internal routing signals and up to six PLL outputs. Figure 2-7. Primary Clocks for LA-MachXO256 and LA-MachXO640 Devices
12 4
16:1
Primary Clock 0
16:1
Primary Clock 1
16:1
Primary Clock 2
16:1
Primary Clock 3
Routing
Clock Pads
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Architecture LA-MachXO Automotive Family Data Sheet
Figure 2-8. Primary Clocks for LA-MachXO1200 and LA-MachXO2280 Devices www..com
Up to 9 4 Up to 6
16:1
Primary Clock 0
Primary Clock 1
16:1
16:1
Primary Clock 2
16:1
Primary Clock 3
Routing
Clock Pads
PLL Outputs
Four secondary clocks are generated from four 16:1 muxes as shown in Figure 2-9. Four of the secondary clock sources come from dual function clock pins and 12 come from internal routing. Figure 2-9. Secondary Clocks for LA-MachXO Devices
12 4
16:1
16:1
Secondary (Control) Clocks
16:1
16:1
Routing
Clock Pads
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Architecture LA-MachXO Automotive Family Data Sheet
The LA-MachXO1200 and LA-MachXO2280 provide PLL support. The source of the PLL input divider can come from an external pin or from internal routing. There are four sources of feedback signals to the feedback divider: from CLKINTFB (internal feedback port), from the global clock nets, from the output of the post scalar divider, and from the routing (or from an external pin). There is a PLL_LOCK signal to indicate that the PLL has locked on to the input clock signal. Figure 2-10 shows the sysCLOCK PLL diagram. The setup and hold times of the device can be improved by programming a delay in the feedback or input path of the PLL which will advance or delay the output clock with reference to the input clock. This delay can be either programmed during configuration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after adjustment and not relock until the tLOCK parameter has been satisfied. Additionally, the phase and duty cycle block allows the user to adjust the phase and duty cycle of the CLKOS output. The sysCLOCK PLLs provide the ability to synthesize clock frequencies. Each PLL has four dividers associated with it: input clock divider, feedback divider, post scalar divider, and secondary clock divider. The input clock divider is used to divide the input clock signal, while the feedback divider is used to multiply the input clock signal. The post scalar divider allows the VCO to operate at higher frequencies than the clock output, thereby increasing the frequency range. The secondary divider is used to derive lower frequency outputs. Figure 2-10. PLL Diagram
Dynamic Delay Adjustment LOCK RST CLKI (from routing or external pin)
Input Clock Divider (CLKI)
Delay Adjust
Voltage Controlled VCO Oscillator
Post Scalar Divider (CLKOP)
Phase/Duty Select
CLKOS
CLKOP Feedback Divider (CLKFB) Secondary Clock Divider (CLKOK)
CLKFB (from Post Scalar Divider output, clock net, routing/external pin or CLKINTFB port
CLKOK
CLKINTFB (internal feedback)
Figure 2-11 shows the available macros for the PLL. Table 2-5 provides signal description of the PLL Block. Figure 2-11. PLL Primitive
RST CLKI CLKFB DDA MODE DDAIZR DDAILAG DDAIDEL[2:0] CLKOP CLKOS
EHXPLLC
CLKOK LOCK CLKINTFB
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Table 2-5. PLL Signal Descriptions www..com
Signal CLKI CLKFB RST CLKOS CLKOP CLKOK LOCK CLKINTFB DDAMODE DDAIZR DDAILAG DDAIDEL[2:0] I/O I I I O O O O O I I I I
Architecture LA-MachXO Automotive Family Data Sheet
Description Clock input from external pin or routing PLL feedback input from PLL output, clock net, routing/external pin or internal feedback from CLKINTFB port "1" to reset the input clock divider PLL output clock to clock tree (phase shifted/duty cycle changed) PLL output clock to clock tree (No phase shift) PLL output to clock tree through secondary clock divider "1" indicates PLL LOCK to CLKI Internal feedback source, CLKOP divider output before CLOCKTREE Dynamic Delay Enable. "1": Pin control (dynamic), "0": Fuse Control (static) Dynamic Delay Zero. "1": delay = 0, "0": delay = on Dynamic Delay Lag/Lead. "1": Lag, "0": Lead Dynamic Delay Input
For more information on the PLL, please see details of additional technical documentation at the end of this data sheet.
sysMEM Memory
The LA-MachXO1200 and LA-MachXO2280 devices contain sysMEM Embedded Block RAMs (EBRs). The EBR consists of a 9-Kbit RAM, with dedicated input and output registers. sysMEM Memory Block The sysMEM block can implement single port, dual port, pseudo dual port, or FIFO memories. Each block can be used in a variety of depths and widths as shown in Table 2-6. Table 2-6. sysMEM Block Configurations
Memory Mode Configurations 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 256 x 36 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 256 x 36 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 256 x 36
Single Port
True Dual Port
Pseudo Dual Port
FIFO
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Architecture LA-MachXO Automotive Family Data Sheet
Bus Size Matching www..com All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to MSB word 0, LSB word 1 to MSB word 1 and so on. Although the word size and number of words for each port varies, this mapping scheme applies to each port. RAM Initialization and ROM Operation If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a ROM. Memory Cascading Larger and deeper blocks of RAMs can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade memory transparently, based on specific design inputs. Single, Dual, Pseudo-Dual Port and FIFO Modes Figure 2-12 shows the five basic memory configurations and their input/output names. In all the sysMEM RAM modes, the input data and address for the ports are registered at the input of the memory array. The output data of the memory is optionally registered at the memory array output. Figure 2-12. sysMEM Memory Primitives
ADA[12:0] DIA[17:0] CLKA CEA DO[35:0] RSTA WEA CSA[2:0] DOA[17:0]
AD[12:0] DI[35:0] CLK CE RST WE CS[2:0]
EBR
EBR
ADB[12:0] DIB[17:0] CEB CLKB RSTB WEB CSB[2:0] DOB[17:0]
Single Port RAM
True Dual Port RAM
AD[12:0] CLK CE RST CS[2:0]
EBR
ADW[12:0] DI[35:0] CLKW CEW DO[35:0] WE RST CS[2:0]
ADR[12:0]
EBR
DO[35:0] CER CLKR
ROM
Pseudo-Dual Port RAM
DI[35:0] CLKW RSTA WE CEW
EBR
DO[35:0] CLKR RSTB RE RCE FF AF EF AE
FIFO
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Architecture LA-MachXO Automotive Family Data Sheet
The EBR memory supports three forms of write behavior for single or dual port operation: www..com 1. Normal - data on the output appears only during the read cycle. During a write cycle, the data (at the current address) does not appear on the output. This mode is supported for all data widths. 2. Write Through - a copy of the input data appears at the output of the same port. This mode is supported for all data widths. 3. Read-Before-Write - when new data is being written, the old contents of the address appears at the output. This mode is supported for x9, x18 and x36 data widths. FIFO Configuration The FIFO has a write port with Data-in, CEW, WE and CLKW signals. There is a separate read port with Data-out, RCE, RE and CLKR signals. The FIFO internally generates Almost Full, Full, Almost Empty and Empty Flags. The Full and Almost Full flags are registered with CLKW. The Empty and Almost Empty flags are registered with CLKR. The range of programming values for these flags are in Table 2-7. Table 2-7. Programmable FIFO Flag Ranges
Flag Name Full (FF) Almost Full (AF) Almost Empty (AE) Empty (EF)
N = Address bit width
Programming Range 1 to (up to 2N-1) 1 to Full-1 1 to Full-1 0
The FIFO state machine supports two types of reset signals: RSTA and RSTB. The RSTA signal is a global reset that clears the contents of the FIFO by resetting the read/write pointer and puts the FIFO flags in their initial reset state. The RSTB signal is used to reset the read pointer. The purpose of this reset is to retransmit the data that is in the FIFO. In these applications it is important to keep careful track of when a packet is written into or read from the FIFO. Memory Core Reset The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A and Port B respectively. The Global Reset (GSRN) signal resets both ports. The output data latches and associated resets for both ports are as shown in Figure 2-13.
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Figure 2-13. Memory Core Reset www..com
Architecture LA-MachXO Automotive Family Data Sheet
Memory Core
D
SET
Q
Port A[17:0]
LCLR
Output Data Latches
D
SET
Q
Port B[17:0]
LCLR
RSTA
RSTB GSRN Programmable Disable
For further information on the sysMEM EBR block, see the details of additional technical documentation at the end of this data sheet. EBR Asynchronous Reset EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the reset is applied and released a clock cycle after the reset is released, as shown in Figure 2-14. The GSR input to the EBR is always asynchronous. Figure 2-14. EBR Asynchronous Reset (Including GSR) Timing Diagram
Reset
Clock
Clock Enable
If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after the EBR read and write clock inputs are in a steady state condition for a minimum of 1/fMAX (EBR clock). The reset release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge. If an EBR is pre-loaded during configuration, the GSR input must be disabled or the release of the GSR during device Wake Up must occur before the release of the device I/Os becoming active. These instructions apply to all EBR RAM, ROM and FIFO implementations. For the EBR FIFO mode, the GSR signal is always enabled and the WE and RE signals act like the clock enable signals in Figure 2-14. The reset timing rules apply to the RPReset input vs the RE input and the RST input vs. the WE and RE inputs. Both RST and RPReset are always asynchronous EBR inputs. Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled.
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Architecture LA-MachXO Automotive Family Data Sheet
PIO Groups www..com
On the LA-MachXO devices, PIO cells are assembled into two different types of PIO groups, those with four PIO cells and those with six PIO cells. PIO groups with four IOs are placed on the left and right sides of the device while PIO groups with six IOs are placed on the top and bottom. The individual PIO cells are connected to their respective sysIO buffers and PADs. On all LA-MachXO devices, two adjacent PIOs can be joined to provide a complementary Output driver pair. The I/ O pin pairs are labeled as "T" and "C" to distinguish between the true and complement pins. The LA-MachXO1200 and LA-MachXO2280 devices contain enhanced I/O capability. All PIO pairs on these larger devices can implement differential receivers. In addition, half of the PIO pairs on the left and right sides of these devices can be configured as LVDS transmit/receive pairs. PIOs on the top of these larger devices also provide PCI support. Figure 2-15. Group of Four Programmable I/O Cells
This structure is used on the left and right of MachXO devices
PIO A
PADA "T"
PIO B Four PIOs PIO C
PADB "C"
PADC "T"
PIO D
PADD "C"
Figure 2-16. Group of Six Programmable I/O Cells
This structure is used on the top and bottom of MachXO devices
PIO A
PADA "T"
PIO B
PADB "C"
PIO C Six PIOs PIO D
PADC "T"
PADD "C"
PIO E
PADE "T"
PIO F
PADF "C"
PIO
The PIO blocks provide the interface between the sysIO buffers and the internal PFU array blocks. These blocks receive output data from the PFU array and a fast output data signal from adjacent PFUs. The output data and fast
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Architecture LA-MachXO Automotive Family Data Sheet
output data signals are multiplexed and provide a single signal to the I/O pin via the sysIO buffer. Figure 2-17 www..com shows the LA-MachXO PIO logic. The tristate control signal is multiplexed from the output data signals and their complements. In addition a global signal (TSALL) from a dedicated pad can be used to tristate the sysIO buffer. The PIO receives an input signal from the pin via the sysIO buffer and provides this signal to the core of the device. In addition there are programmable elements that can be utilized by the design tools to avoid positive hold times. Figure 2-17. LA-MachXO PIO Block Diagram
From Routing
TS
TSALL
From Routing sysIO Buffer Fast Output Data signal DO TO
PAD
1 Input Data Signal 2 3 4+
Programmable Delay Elements
Note: Buffer 1 tracks with VCCAUX Buffer 2 tracks with VCCIO. Buffer 3 tracks with internal 1.2V VREF. Buffer 4 is available in MachXO1200 and MachXO2280 devices only.
From Complementary Pad
sysIO Buffer
Each I/O is associated with a flexible buffer referred to as a sysIO buffer. These buffers are arranged around the periphery of the device in groups referred to as Banks. The sysIO buffers allow users to implement the wide variety of standards that are found in today's systems including LVCMOS, TTL, BLVDS, LVDS and LVPECL. In the LA-MachXO devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS and PCI) are powered using VCCIO. In addition to the Bank VCCIO supplies, the LA-MachXO devices have a VCC core logic power supply, and a VCCAUX supply that powers up a variety of internal circuits including all the differential and referenced input buffers. LA-MachXO256 and LA-MachXO640 devices contain single-ended input buffers and single-ended output buffers with complementary outputs on all the I/O Banks. LA-MachXO1200 and LA-MachXO2280 devices contain two types of sysIO buffer pairs. 1. Top and Bottom sysIO Buffer Pairs The sysIO buffer pairs in the top and bottom Banks of the device consist of two single-ended output drivers and two sets of single-ended input buffers (for ratioed or absolute input levels). The I/O pairs on the top and bottom
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Lattice Semiconductor
of the devices also www..com
Architecture LA-MachXO Automotive Family Data Sheet
support differential input buffers. PCI clamps are available on the top Bank I/O buffers. The PCI clamp is enabled after VCC, VCCAUX, and VCCIO are at valid operating levels and the device has been configured. The two pads in the pair are described as "true" and "comp", where the true pad is associated with the positive side of the differential input buffer and the comp (complementary) pad is associated with the negative side of the differential input buffer.
2. Left and Right sysIO Buffer Pairs The sysIO buffer pairs in the left and right Banks of the device consist of two single-ended output drivers and two sets of single-ended input buffers (supporting ratioed and absolute input levels). The devices also have a differential driver per output pair. The referenced input buffer can also be configured as a differential input buffer. In these Banks the two pads in the pair are described as "true" and "comp", where the true pad is associated with the positive side of the differential I/O, and the comp (complementary) pad is associated with the negative side of the differential I/O. Typical I/O Behavior During Power-up The internal power-on-reset (POR) signal is deactivated when VCC and VCCAUX have reached satisfactory levels. After the POR signal is deactivated, the FPGA core logic becomes active. It is the user's responsibility to ensure that all VCCIO Banks are active with valid input logic levels to properly control the output logic states of all the I/O Banks that are critical to the application. The default configuration of the I/O pins in a blank device is tri-state with a weak pull-up to VCCIO. The I/O pins will maintain the blank configuration until VCC, VCCAUX and VCCIO have reached satisfactory levels at which time the I/Os will take on the user-configured settings. The VCC and VCCAUX supply the power to the FPGA core fabric, whereas the VCCIO supplies power to the I/O buffers. In order to simplify system design while providing consistent and predictable I/O behavior, the I/O buffers should be powered up along with the FPGA core fabric. Therefore, VCCIO supplies should be powered up before or together with the VCC and VCCAUX supplies Supported Standards The LA-MachXO sysIO buffer supports both single-ended and differential standards. Single-ended standards can be further subdivided into LVCMOS and LVTTL. The buffer supports the LVTTL, LVCMOS 1.2, 1.5, 1.8, 2.5, and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individually configurable options for drive strength, bus maintenance (weak pull-up, weak pull-down, bus-keeper latch or none) and open drain. BLVDS and LVPECL output emulation is supported on all devices. The LA-MachXO1200 and LA-MachXO2280 support on-chip LVDS output buffers on approximately 50% of the I/Os on the left and right Banks. Differential receivers for LVDS, BLVDS and LVPECL are supported on all Banks of LA-MachXO1200 and LA-MachXO2280 devices. PCI support is provided in the top Banks of the LA-MachXO1200 and LA-MachXO2280 devices. Table 2-8 summarizes the I/O characteristics of the devices in the LA-MachXO family. Tables 2-9 and 2-10 show the I/O standards (together with their supply and reference voltages) supported by the LA-MachXO devices. For further information on utilizing the sysIO buffer to support a variety of standards please see the details of additional technical documentation at the end of this data sheet.
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Lattice Semiconductor
Table 2-8. I/O Support Device by Device www..com
LA-MachXO256 Number of I/O Banks 2 Single-ended (all I/O Banks) Type of Input Buffers 4
Architecture LA-MachXO Automotive Family Data Sheet
LA-MachXO640 8 Single-ended (all I/O Banks)
LA-MachXO1200 8 Single-ended (all I/O Banks) Differential Receivers (all I/O Banks)
LA-MachXO2280 Single-ended (all I/O Banks) Differential Receivers (all I/O Banks) Single-ended buffers with complementary outputs (all I/O Banks)
Single-ended buffers with complementary outputs (all I/O Banks) Types of Output Buffers
Single-ended buffers with complementary outputs (all I/O Banks)
Single-ended buffers with complementary outputs (all I/O Banks)
Differential buffers with Differential buffers with true LVDS outputs (50% true LVDS outputs (50% on left and right side) on left and right side) Differential Output Emulation Capability PCI Support All I/O Banks No All I/O Banks No All I/O Banks Top side only All I/O Banks Top side only
Table 2-9. Supported Input Standards
VCCIO (Typ.) Input Standard Single Ended Interfaces LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 PCI1 Differential Interfaces BLVDS2, LVDS2, LVPECL2, RSDS2
1. Top Banks of LA-MachXO1200 and LA-MachXO2280 devices only. 2. LA-MachXO1200 and LA-MachXO2280 devices only.
3.3V
2.5V
1.8V
1.5V
1.2V

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Lattice Semiconductor
Table 2-10. Supported Output Standards www..com
Output Standard Single-ended Interfaces LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 LVCMOS33, Open Drain LVCMOS25, Open Drain LVCMOS18, Open Drain LVCMOS15, Open Drain LVCMOS12, Open Drain PCI333 Differential Interfaces LVDS1, 2 BLVDS, RSDS LVPECL2
2
Architecture LA-MachXO Automotive Family Data Sheet
Drive 4mA, 8mA, 12mA, 16mA 4mA, 8mA, 12mA, 14mA 4mA, 8mA, 12mA, 14mA 4mA, 8mA, 12mA, 14mA 4mA, 8mA 2mA, 6mA 4mA, 8mA, 12mA, 14mA 4mA, 8mA, 12mA, 14mA 4mA, 8mA, 12mA, 14mA 4mA, 8mA 2mA, 6mA N/A N/A N/A N/A
VCCIO (Typ.) 3.3 3.3 2.5 1.8 1.5 1.2 -- -- -- -- -- 3.3 2.5 2.5 3.3
1. LA-MachXO1200 and LA-MachXO2280 devices have dedicated LVDS buffers. 2. These interfaces can be emulated with external resistors in all devices. 3. Top Banks of LA-MachXO1200 and LA-MachXO2280 devices only.
sysIO Buffer Banks
The number of Banks vary between the devices of this family. Eight Banks surround the two larger devices, the LAMachXO1200 and LA-MachXO2280 (two Banks per side). The LA-MachXO640 has four Banks (one Bank per side). The smallest member of this family, the LA-MachXO256, has only two Banks. Each sysIO buffer Bank is capable of supporting multiple I/O standards. Each Bank has its own I/O supply voltage (VCCIO) which allows it to be completely independent from the other Banks. Figure 2-18, Figure 2-18, Figure 2-20 and Figure 2-21 shows the sysIO Banks and their associated supplies for all devices.
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Lattice Semiconductor
Figure 2-18. LA-MachXO2280t Banks. www.DataShee 4U
com
Architecture LA-MachXO Automotive Family Data Sheet
GND
VCCIO0
1 1
VCCIO1
35 1
GND
36 1
Bank 0
Bank 1
Bank 7
VCCIO7 GND
VCCIO2 GND
Bank 2
34 1
34 1
Bank 6
VCCIO6 GND
VCCIO3 GND
Bank 3
33 1
Bank 5
31
1
Bank 4
33 35
VCCIO5
VCCIO4
Figure 2-19. LA-MachXO1200 Banks
GND VCCIO0
1 1
GND
Bank 0
24
1
GND
VCCIO1
Bank 1
GND
30 1
Bank 7
VCCIO7 GND
VCCIO2 GND
Bank 2
26 1
26 1
Bank 6
VCCIO6 GND
VCCIO3 GND
Bank 3
28 1
Bank 5
20
1
Bank 4
28 29
VCCIO5
VCCIO4
GND
2-19
GND
Lattice Semiconductor
Figure 2-20. LA-MachXO640 Banks www..com
V CCO0
Architecture LA-MachXO Automotive Family Data Sheet
GND
1 1
Bank 0
42 1
Bank 3
V CCO3 GND
V CCO1 GND
Bank 1
40 1
Bank 2
40 37
VCCO2
Figure 2-21. LA-MachXO256 Banks
GND
V CCO0
1 1
Bank 0
GND
Bank 1 GND V CCO1
41 37
Hot Socketing
The LA-MachXO automotive devices have been carefully designed to ensure predictable behavior during powerup and power-down. Leakage into I/O pins is controlled to within specified limits. This allows for easy integration
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Architecture LA-MachXO Automotive Family Data Sheet
with the rest of the system. These capabilities make the LA-MachXO ideal for many multiple power supply and www..com hot-swap applications.
Sleep Mode
The LA-MachXO "C" devices (VCC = 1.8/2.5/3.3V) have a sleep mode that allows standby current to be reduced dramatically during periods of system inactivity. Entry and exit to Sleep mode is controlled by the SLEEPN pin. During Sleep mode, the logic is non-operational, registers and EBR contents are not maintained, and I/Os are tristated. Do not enter Sleep mode during device programming or configuration operation. In Sleep mode, power supplies are in their normal operating range, eliminating the need for external switching of power supplies. Table 2-11 compares the characteristics of Normal, Off and Sleep modes. Table 2-11. Characteristics of Normal, Off and Sleep Modes
Characteristic SLEEPN Pin Static Icc I/O Leakage Power Supplies VCC/VCCIO/VCCAUX Logic Operation I/O Operation JTAG and Programming circuitry EBR Contents and Registers Normal High Typical <10mA <10A Normal Range User Defined User Defined Operational Maintained Off -- 0 <1mA 0 Non Operational Tri-state Non-operational Non-maintained Sleep Low Typical <100uA <10A Normal Range Non operational Tri-state Non-operational Non-maintained
SLEEPN Pin Characteristics
The SLEEPN pin behaves as an LVCMOS input with the voltage standard appropriate to the VCC supply for the device. This pin also has a weak pull-up, along with a Schmidt trigger and glitch filter to prevent false triggering. An external pull-up to VCC is recommended when Sleep Mode is not used to ensure the device stays in normal operation mode. Typically, the device enters sleep mode several hundred nanoseconds after SLEEPN is held at a valid low and restarts normal operation as specified in the Sleep Mode Timing table. The AC and DC specifications portion of this data sheet shows a detailed timing diagram.
Oscillator
Every LA-MachXO device has an internal CMOS oscillator. The oscillator can be routed as an input clock to the clock tree or to general routing resources. The oscillator frequency can be divided by internal logic. There is a dedicated programming bit to enable/disable the oscillator. The oscillator frequency ranges from 16MHz to 26MHz.
Configuration and Testing
The following section describes the configuration and testing features of the LA-MachXO automotive family of devices.
IEEE 1149.1-Compliant Boundary Scan Testability
All LA-MachXO devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test access port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port shares its power supply with one of the VCCIO Banks (LA-MachXO256: VCCIO1; LA-MachXO640: VCCIO2; LA-MachXO1200 and LAMachXO2280: VCCIO5) and can operate with LVCMOS3.3, 2.5, 1.8, 1.5, and 1.2 standards. For more details on boundary scan test, please see information regarding additional technical documentation at the end of this data sheet. 2-21
Lattice Semiconductor Device Configuration www..com
Architecture LA-MachXO Automotive Family Data Sheet
All LA-MachXO devices contain a test access port that can be used for device configuration and programming. The non-volatile memory in the LA-MachXO can be configured in two different modes: * In IEEE 1532 mode via the IEEE 1149.1 port. In this mode, the device is off-line and I/Os are controlled by BSCAN registers. * In background mode via the IEEE 1149.1 port. This allows the device to remain operational in user mode while reprogramming takes place. The SRAM configuration memory can be configured in three different ways: * At power-up via the on-chip non-volatile memory. * After a refresh command is issued via the IEEE 1149.1 port. * In IEEE 1532 mode via the IEEE 1149.1 port. Figure 2-22 provides a pictorial representation of the different programming modes available in the LA-MachXO devices. On power-up, the SRAM is ready to be configured with IEEE 1149.1 serial TAP port using IEEE 1532 protocols. Leave Alone I/O When using IEEE 1532 mode for non-volatile memory programming, SRAM configuration, or issuing a refresh command, users may specify I/Os as high, low, tristated or held at current value. This provides excellent flexibility for implementing systems where reconfiguration or reprogramming occurs on-the-fly. TransFR (Transparent Field Reconfiguration) TransFR (TFR) is a unique Lattice technology that allows users to update their logic in the field without interrupting system operation using a single ispVM command. See Lattice technical note #TN1087, Minimizing System Interruption During Configuration Using TransFR Technology, for details. Security The LA-MachXO automotive devices contain security bits that, when set, prevent the readback of the SRAM configuration and non-volatile memory spaces. Once set, the only way to clear the security bits is to erase the memory space. For more information on device configuration, please see details of additional technical documentation at the end of this data sheet.
AEC-Q100 Tested and Qualified
The Automotive Electronics Council (AEC) consists of two committees: the Quality Systems Committee and the Component Technical Committee. These committees are composed of representatives from sustaining and other associate members. The AEC Component Technical Committee is the standardization body for establishing standards for reliable, high quality electronic components. In particular, the AEC-Q100 specification "Stress Test for Qualification for Integrated Circuits" defines qualification and re-qualification requirements for electronic components. Components meeting these specifications are suitable for use in the harsh automotive environment without additional component-level qualification testing. Lattice's LA-ispMACH 4000V and LA-MachXO devices completed and passed the requirements of the AEC-Q100 specification.
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Architecture LA-MachXO Automotive Family Data Sheet
Figure 2-22. LA-MachXO Configuration and Programming www..com
ISP 1149.1 TAP Port Port
Background
1532
Mode Program in seconds Non-Volatile Memory Space Refresh Download in microseconds Power-up Configure in milliseconds SRAM Memory Space
Density Shifting
The LA-MachXO family has been designed to enable density migration in the same package. Furthermore, the architecture ensures a high success rate when performing design migration from lower density parts to higher density parts. In many cases, it is also possible to shift a lower utilization design targeted for a high-density device to a lower density device. However, the exact details of the final resource utilization will impact the likely success in each case.
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LA-MachXO Automotive Family Data Sheet DC and Switching Characteristics
Data Sheet DS1003
November 2007
Absolute Maximum Ratings1, 2, 3
LCMXO E (1.2V) LCMXO C (1.8V/2.5V/3.3V) Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 1.32V . . . . . . . . . . . . . . . -0.5 to 3.75V Supply Voltage VCCAUX . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.75V . . . . . . . . . . . . . . . -0.5 to 3.75V Output Supply Voltage VCCIO . . . . . . . . . . . . . . . . -0.5 to 3.75V . . . . . . . . . . . . . . . -0.5 to 3.75V I/O Tristate Voltage Applied 4 . . . . . . . . . . . . . . . . . -0.5 to 3.75V . . . . . . . . . . . . . . . -0.5 to 3.75V Dedicated Input Voltage Applied4 . . . . . . . . . . . . . -0.5 to 3.75V . . . . . . . . . . . . . . . -0.5 to 4.25V Storage Temperature (ambient). . . . . . . . . . . . . . . -65 to 150C . . . . . . . . . . . . . . . -65 to 150C Junction Temp. (Tj) . . . . . . . . . . . . . . . . . . . . . . . . . . +125C . . . . . . . . . . . . . . . . . . . +125C
1. Stress above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 2. Compliance with the Lattice Thermal Management document is required. 3. All voltages referenced to GND. 4. Overshoot and undershoot of -2V to (VIHMAX + 2) volts is permitted for a duration of <20ns.
Recommended Operating Conditions1
Symbol VCC VCCAUX VCCIO2 tJAUTO
3
Parameter Core Supply Voltage for 1.2V Devices Core Supply Voltage for 1.8V/2.5V/3.3V Devices Auxiliary Supply Voltage I/O Driver Supply Voltage Junction Temperature Automotive Operation
Min. 1.14 1.71 3.135 1.14 -40 -40
Max. 1.26 3.465 3.465 3.465 125 125
Units V V V V
o o
C C
tJFLASHAUTO Junction Temperature, Flash Programming, Automotive
1. Like power supplies must be tied together. For example, if VCCIO and VCC are both 2.5V, they must also be the same supply. 3.3V VCCIO and 1.2V VCCIO should be tied to VCCAUX or 1.2V VCC respectively. 2. See recommended voltages by I/O standard in subsequent table. 3. VCC must reach minimum VCC value before VCCAUX reaches 2.5V.
LA-MachXO256 and LA-MachXO640 Hot Socketing Specifications1, 2, 3
Symbol IDK Parameter Input or I/O leakage Current Condition 0 VIN VIH (MAX) Min. -- Typ. -- Max +/-1000 Units A
1. Insensitive to sequence of VCC, VCCAUX, and VCCIO. However, assumes monotonic rise/fall rates for VCC, VCCAUX, and VCCIO. 2. 0 VCC VCC (MAX), 0 VCCIO VCCIO (MAX) and 0 VCCAUX VCCAUX (MAX). 3. IDK is additive to IPU, IPD or IBH.
(c) 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
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DS1003 DC and Switching_01.3
Lattice Semiconductor
DC and Switching Characteristics LA-MachXO Automotive Family Data Sheet
www..com LA-MachXO1200 and LA-MachXO2280 Hot Socketing Specifications1, 2, 3, 4
Symbol IDK
Parameter Input or I/O Leakage Current
Condition 0 VIN VIH (MAX.) VIN VCCIO VIN > VCCIO
Min. -- -- --
Typ. -- -- 35
Max. +/-1000 +/-1000 --
Units A A mA
Non-LVDS General Purpose sysIOs LVDS General Purpose sysIOs IDK_LVDS
1. 2. 3. 4.
Input or I/O Leakage Current
Insensitive to sequence of VCC, VCCAUX, and VCCIO. However, assumes monotonic rise/fall rates for VCC, VCCAUX, and VCCIO. 0 VCC VCC (MAX), 0 VCCIO VCCIO (MAX), and 0 VCCAUX VCCAUX (MAX). IDK is additive to IPU, IPW or IBH. LVCMOS and LVTTL only.
DC Electrical Characteristics
Over Recommended Operating Conditions
Symbol Parameter Condition 0 VIN (VCCIO - 0.2V) (VCCIO - 0.2V) < VIN 3.6V 0 VIN 0.7 VCCIO VIL (MAX) VIN VIH (MAX) VIN = VIL (MAX) 0 VIN VIH (MAX) 0 VIN VIH (MAX) 0 VIN VIH (MAX) VCCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, VCC = Typ., VIO = 0 to VIH (MAX) VCCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, VCC = Typ., VIO = 0 to VIH (MAX) Min. -- -- -30 30 30 -30 -- -- VIL (MAX) -- -- Typ. -- -- -- -- -- -- -- -- -- 8 8 Max. 10 40 -150 150 -- -- 150 -150 VIH (MIN) -- -- Units A A A A A A A A V pf pf
IIL, IIH1, 4, 5 Input or I/O Leakage IPU IPD IBHLS IBHHS IBHLO IBHHO VBHT3 C1 C2 I/O Active Pull-up Current I/O Active Pull-down Current Bus Hold Low sustaining current Bus Hold Low Overdrive current Bus Hold High Overdrive current Bus Hold trip Points I/O Capacitance2 Dedicated Input Capacitance2
Bus Hold High sustaining current VIN = 0.7VCCIO
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured with the output driver active. Bus maintenance circuits are disabled. 2. TA 25C, f = 1.0MHz 3. Please refer to VIL and VIH in the sysIO Single-Ended DC Electrical Characteristics table of this document. 4. Not applicable to SLEEPN pin. 5. When VIH is higher than VCCIO, a transient current typically of 30ns in duration or less with a peak current of 6mA can occur on the high-tolow transition. For LA-MachXO1200 and LA-MachXO2280 true LVDS output pins, VIH must be less than or equal to VCCIO.
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Lattice Semiconductor
DC and Switching Characteristics LA-MachXO Automotive Family Data Sheet
Supply Current (Sleep Mode)1, 2 www..com
Symbol ICC ICCAUX ICCIO
1. 2. 3. 4.
Parameter Core Power Supply Auxiliary Power Supply Bank Power Supply4 LCMXO256C LCMXO640C LCMXO256C LCMXO640C
Device
Typ.3 12 12 1 1 2
Max. 25 25 15 25 30
Units A A A A A
All LCMXO `C' Devices
Assumes all inputs are configured as LVCMOS and held at the VCCIO or GND. Frequency = 0MHz. TA = 25C, power supplies at nominal voltage. Per Bank.
Supply Current (Standby)1, 2, 3, 4
Over Recommended Operating Conditions
Symbol Parameter Device LCMXO256C LCMXO640C ICC Core Power Supply LCMXO256E LCMXO640E LCMXO1200E LCMXO2280E LCMXO256E/C ICCAUX Auxiliary Power Supply VCCAUX = 3.3V Bank Power Supply
6
Typ.5 7 9 4 6 10 12 5 7 12 13 2
Units mA mA mA mA mA mA mA mA mA mA mA
LCMXO640E/C LCMXO1200E LCMXO2280E All devices
ICCIO
1. 2. 3. 4. 5. 6.
For further information on supply current, please see details of additional technical documentation at the end of this data sheet. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at VCCIO or GND. Frequency = 0MHz. User pattern = blank. TJ = 25oC, power supplies at nominal voltage. Per Bank. VCCIO = 2.5V. Does not include pull-up/pull-down.
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Lattice Semiconductor
www..com Initialization Supply Current1, 2, 3, 4
DC and Switching Characteristics LA-MachXO Automotive Family Data Sheet
Over Recommended Operating Conditions
Symbol Parameter Device LCMXO256C LCMXO640C ICC Core Power Supply LCMXO256E LCMXO640E LCMXO1200E LCMXO2280E LCMXO256E/C ICCAUX Auxiliary Power Supply VCCAUX = 3.3V Bank Power Supply
6
Typ.5 13 17 10 14 18 20 10 13 24 25 2
Units mA mA mA mA mA mA mA mA mA mA mA
LCMXO640E/C LCMXO1200E LCMXO2280E All devices
ICCIO
1. 2. 3. 4. 5. 6.
For further information on supply current, please see details of additional technical documentation at the end of this data sheet. Assumes all I/O pins are held at VCCIO or GND. Frequency = 0MHz. Typical user pattern. TJ = 25oC, power supplies at nominal voltage. Per Bank, VCCIO = 2.5V. Does not include pull-up/pull-down.
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Lattice Semiconductor
DC and Switching Characteristics LA-MachXO Automotive Family Data Sheet
Programming and Erase Flash Supply Current1, 2, 3, 4 www..com
Symbol Parameter Device LCMXO256C LCMXO640C ICC Core Power Supply LCMXO256E LCMXO640E LCMXO1200E LCMXO2280E LCMXO256E/C ICCAUX Auxiliary Power Supply VCCAUX = 3.3V Bank Power Supply
6
Typ.5 9 11 6 8 12 14 8 10 15 16 2
Units mA mA mA mA mA mA mA mA mA mA mA
LCMXO640E/C LCMXO1200E LCMXO2280E All devices
ICCIO
1. 2. 3. 4. 5. 6.
For further information on supply current, please see details of additional technical documentation at the end of this data sheet. Assumes all I/O pins are held at VCCIO or GND. Typical user pattern. JTAG programming is at 25MHz. TJ = 25C, power supplies at nominal voltage. Per Bank. VCCIO = 2.5V. Does not include pull-up/pull-down.
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Lattice Semiconductor
DC and Switching Characteristics LA-MachXO Automotive Family Data Sheet
sysIO Recommended Operating Conditions www..com
VCCIO (V) Standard LVCMOS 3.3 LVCMOS 2.5 LVCMOS 1.8 LVCMOS 1.5 LVCMOS 1.2 LVTTL PCI3 LVDS1, 2 LVPECL1 BLVDS RSDS1
1
Min. 3.135 2.375 1.71 1.425 1.14 3.135 3.135 2.375 3.135 2.375 2.375
Typ. 3.3 2.5 1.8 1.5 1.2 3.3 3.3 2.5 3.3 2.5 2.5
Max. 3.465 2.625 1.89 1.575 1.26 3.465 3.465 2.625 3.465 2.625 2.625
1. Inputs on chip. Outputs are implemented with the addition of external resistors. 2. MachXO1200 and MachXO2280 devices have dedicated LVDS buffers 3. Input on the top bank of the MachXO1200 and MachXO2280 only.
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Lattice Semiconductor
DC and Switching Characteristics LA-MachXO Automotive Family Data Sheet
sysIO Single-Ended DC Electrical Characteristics www..com
Input/Output Standard LVCMOS 3.3 VIL Min. (V) -0.3 Max. (V) 0.8 VIH Min. (V) 2.0 VOL Max. (V) Max. (V) 3.6 0.4 0.2 0.4 LVTTL -0.3 0.8 2.0 3.6 0.4 0.2 LVCMOS 2.5 LVCMOS 1.8 LVCMOS 1.5 LVCMOS 1.2 ("C" Version) LVCMOS 1.2 ("E" Version) PCI -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 0.7 0.35VCCIO 0.35VCCIO 0.42 0.35VCC 0.3VCCIO 1.7 0.65VCCIO 0.65VCCIO 0.78 0.65VCC 0.5VCCIO 3.6 3.6 3.6 3.6 3.6 3.6 0.4 0.2 0.4 0.2 0.4 0.2 0.4 0.2 0.4 0.2 0.1VCCIO VOH Min. (V) VCCIO - 0.4 VCCIO - 0.2 2.4 VCCIO - 0.4 VCCIO - 0.2 VCCIO - 0.4 VCCIO - 0.2 VCCIO - 0.4 VCCIO - 0.2 VCCIO - 0.4 VCCIO - 0.2 VCCIO - 0.4 VCCIO - 0.2 VCCIO - 0.4 VCCIO - 0.2 0.9VCCIO IOL1 (mA) 16, 12, 8, 4 0.1 16 12, 8, 4 0.1 16, 12, 8, 4 0.1 16, 12, 8, 4 0.1 8, 4 0.1 6, 2 0.1 6, 2 0.1 1.5 IOH1 (mA) -14, -12, -8, -4 -0.1 -16 -12, -8, -4 -0.1 -14, -12, -8, -4 -0.1 -14, -12, -8, -4 -0.1 -8, -4 -0.1 -6, -2 -0.1 -6, -2 -0.1 -0.5
1. The average DC current drawn by I/Os between GND connections, or between the last GND in an I/O Bank and the end of an I/O Bank, as shown in the logic signal connections table shall not exceed n * 8mA. Where n is the number of I/Os between Bank GND connections or between the last GND in a Bank and the end of a Bank.
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Lattice Semiconductor
DC and Switching Characteristics LA-MachXO Automotive Family Data Sheet
sysIO Differential Electrical Characteristics www..com
LVDS
Over Recommended Operating Conditions
Parameter Symbol VINP, VINM VTHD VCM IIN VOH VOL VOD VOD VOS VOS IOSD Parameter Description Input Voltage Differential Input Threshold 100mV VTHD Input Common Mode Voltage Input current Output high voltage for VOP or VOM Output low voltage for VOP or VOM Output voltage differential Change in VOD between high and low Output voltage offset Change in VOS between H and L Output short circuit current VOD = 0V Driver outputs shorted (VOP - VOM)/2, RT = 100 Ohm 200mV VTHD 350mV VTHD Power on RT = 100 Ohm RT = 100 Ohm (VOP - VOM), RT = 100 Ohm Test Conditions Min. 0 +/-100 VTHD/2 VTHD/2 VTHD/2 -- -- 0.9V 250 -- 1.125 -- -- Typ. -- -- 1.2 1.2 1.2 -- 1.38 1.03 350 -- 1.25 -- -- Max. 2.4 -- 1.8 1.9 2.0 +/-10 1.60 -- 450 50 1.375 50 6 Units V mV V V V A V V mV mV V mV mA
LVDS Emulation
LA-MachXO automotive devices can support LVDS outputs via emulation (LVDS25E), in addition to the LVDS support that is available on-chip on certain devices. The output is emulated using complementary LVCMOS outputs in conjunction with resistors across the driver outputs on all devices. The scheme shown in Figure 3-1 is one possible solution for LVDS standard implementation. Resistor values in Figure 3-1 are industry standard values for 1% resistors. Figure 3-1. LVDS Using External Resistors (LVDS25E)
VCCIO = 2.5 158 8mA Zo = 100 VCCIO = 2.5 8mA On-chip Emulated LVDS Buffer
Note: All resistors are 1%.
+ 100 -
158
140
Off-chip
Off-chip
On-chip
The LVDS differential input buffers are available on certain devices in the LA-MachXO family.
3-8
Lattice Semiconductor
Table 3-1. LVDS DC Conditions www..com
DC and Switching Characteristics LA-MachXO Automotive Family Data Sheet
Over Recommended Operating Conditions
Parameter ZOUT RS RP RT VOH VOL VOD VCM ZBACK IDC Description Output impedance Driver series resistor Driver parallel resistor Receiver termination Output high voltage Output low voltage Output differential voltage Output common mode voltage Back impedance DC output current Typical 20 294 121 100 1.43 1.07 0.35 1.25 100 3.66 Units V V V V mA
BLVDS
The LA-MachXO automotive family supports the BLVDS standard through emulation. The output is emulated using complementary LVCMOS outputs in conjunction with a parallel external resistor across the driver outputs. The input standard is supported by the LVDS differential input buffer on certain devices. BLVDS is intended for use when multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-2 is one possible solution for bi-directional multi-point differential signals. Figure 3-2. BLVDS Multi-point Output Example
Heavily loaded backplane, effective Zo ~ 45 to 90 ohms differential 2.5V 80 16mA 80 2.5V 80 16mA 80 + 80 16mA 80 80 + 2.5V 45-90 ohms 45-90 ohms 16mA 2.5V
...
2.5V 16mA
2.5V 16mA
-
2.5V 16mA
2.5V 16mA
-
+
3-9
+
Lattice Semiconductor
Table 3-2. BLVDS DC Conditions1 www..com
DC and Switching Characteristics LA-MachXO Automotive Family Data Sheet
Over Recommended Operating Conditions
Nominal Symbol ZOUT RTLEFT RTRIGHT VOH VOL VOD VCM IDC Description Output impedance Left end termination Right end termination Output high voltage Output low voltage Output differential voltage Output common mode voltage DC output current Zo = 45 100 45 45 1.375 1.125 0.25 1.25 11.2 Zo = 90 100 90 90 1.48 1.02 0.46 1.25 10.2 Units ohm ohm ohm V V V V mA
1. For input buffer, see LVDS table.
LVPECL
The LA-MachXO automotive family supports the differential LVPECL standard through emulation. This output standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs on all the devices. The LVPECL input standard is supported by the LVDS differential input buffer on certain devices. The scheme shown in Figure 3-3 is one possible solution for point-to-point signals. Figure 3-3. Differential LVPECL
VCCIO = 3.3V 100 ohms 16mA VCCIO = 3.3V 100 ohms 16mA Transmission line, Zo = 100 ohm differential On-chip Off-chip Off-chip On-chip + 150 ohms 100 ohms -
Table 3-3. LVPECL DC Conditions1 Over Recommended Operating Conditions
Symbol ZOUT RP RT VOH VOL VOD VCM ZBACK IDC Description Output impedance Driver parallel resistor Receiver termination Output high voltage Output low voltage Output differential voltage Output common mode voltage Back impedance DC output current Nominal 100 150 100 2.03 1.27 0.76 1.65 85.7 12.7 Units ohm ohm ohm V V V V ohm mA
1. For input buffer, see LVDS table.
3-10
Lattice Semiconductor
DC and Switching Characteristics LA-MachXO Automotive Family Data Sheet
For further information on LVPECL, BLVDS and other differential interfaces please see details of additional techniwww..com cal documentation at the end of the data sheet.
RSDS
The LA-MachXO automotive family supports the differential RSDS standard. The output standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs on all the devices. The RSDS input standard is supported by the LVDS differential input buffer on certain devices. The scheme shown in Figure 3-4 is one possible solution for RSDS standard implementation. Use LVDS25E mode with suggested resistors for RSDS operation. Resistor values in Figure 3-4 are industry standard values for 1% resistors. Figure 3-4. RSDS (Reduced Swing Differential Standard)
VCCIO = 2.5V 294 8mA VCCIO = 2.5V 294 8mA On-chip Emulated RSDS Buffer Off-chip Off-chip On-chip Zo = 100 + 121 100 -
Table 3-4. RSDS DC Conditions
Parameter ZOUT RS RP RT VOH VOL VOD VCM ZBACK IDC Description Output impedance Driver series resistor Driver parallel resistor Receiver termination Output high voltage Output low voltage Output differential voltage Output common mode voltage Back impedance DC output current Typical 20 294 121 100 1.35 1.15 0.20 1.25 101.5 3.66 Units ohm ohm ohm ohm V V V V ohm mA
3-11
Lattice Semiconductor
DC and Switching Characteristics LA-MachXO Automotive Family Data Sheet
Typical Building Block Function Performance1 www..com
Pin-to-Pin Performance (LVCMOS25 12mA Drive)
Function Basic Functions 16-bit decoder 4:1 MUX 16:1 MUX 9.4 6.3 7.1 ns ns ns -3 Timing Units
Register-to-Register Performance
Function Basic Functions 16:1 MUX 16-bit adder 16-bit counter 64-bit counter 256x36 Single Port RAM 512x18 True-Dual Port RAM Distributed Memory Functions 16x2 Single Port RAM 64x2 Single Port RAM 128x4 Single Port RAM 32x2 Pseudo-Dual Port RAM 64x4 Pseudo-Dual Port RAM 310 229 186 224 194 MHz MHz MHz MHz MHz 348 209 277 143 203 203 MHz MHz MHz MHz MHz MHz -3 Timing Units
Embedded Memory Functions (1200 and 2280 Devices Only)
1. The above timing numbers are generated using the ispLEVER design tool. Exact performance may vary with device and tool version. The tool uses internal parameters that have been characterized but are not tested on every device. Rev. A 0.19
Derating Logic Timing
Logic Timing provided in the following sections of the data sheet and the ispLEVER design tools are worst case numbers in the operating range. Actual delays may be much faster. The ispLEVER design tool from Lattice can provide logic timing numbers at a particular temperature and voltage.
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Lattice Semiconductor
DC and Switching Characteristics LA-MachXO Automotive Family Data Sheet
LA-MachXO External Switching Characteristics1 www..com
Over Recommended Operating Conditions
-3 Parameter Description Device LCMXO256 tPD Best Case tPD Through 1 LUT LCMXO640 LCMXO1200 LCMXO2280 LCMXO256 tCO Best Case Clock to Output - From PFU LCMXO640 LCMXO1200 LCMXO2280 LCMXO256 tSU Clock to Data Setup - To PFU LCMXO640 LCMXO1200 LCMXO2280 LCMXO256 tH Clock to Data Hold - To PFU LCMXO640 LCMXO1200 LCMXO2280 LCMXO256 fMAX_IO Clock Frequency of I/O and PFU Register LCMXO640 LCMXO1200 LCMXO2280 LCMXO256 tSKEW_PRI Global Clock Skew Across Device LCMXO640 LCMXO1200 LCMXO2280
1. General timing numbers based on LVCMOS2.5V, 12 mA. Rev. A 0.19
Min. -- -- -- -- -- -- -- -- 1.8 1.5 1.6 1.5 -0.3 -0.1 0.0 -0.4 -- -- -- -- -- -- -- --
Max. 4.9 4.9 5.1 5.1 5.6 5.7 6.1 6.1 -- -- -- -- -- -- -- -- 500 500 500 500 240 240 260 260
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz MHz ps ps ps ps
General I/O Pin Parameters (Using Global Clock without PLL)1
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Lattice Semiconductor
DC and Switching Characteristics LA-MachXO Automotive Family Data Sheet
LA-MachXO Internal Timing Parameters1 www..com
Over Recommended Operating Conditions
-3 Parameter PFU/PFF Logic Mode Timing tLUT4_PFU tLUT6_PFU tLSR_PFU tSUM_PFU tHM_PFU tSUD_PFU tHD_PFU tCK2Q_PFU tLE2Q_PFU tLD2Q_PFU tCORAM_PFU tSUDATA_PFU tHDATA_PFU tHADDR_PFU tHWREN_PFU tIN_PIO tOUT_PIO LUT4 delay (A to D inputs to F output) LUT6 delay (A to D inputs to OFX output) Set/Reset to output of PFU Clock to Mux (M0,M1) input setup time Clock to Mux (M0,M1) input hold time Clock to D input setup time Clock to D input hold time Clock to Q delay, D-type register configuration Clock to Q delay latch configuration D to Q throughput delay when latch is enabled Clock to Output Data Setup Time Data Hold Time Address Hold Time Write/Read Enable Hold Time Input Buffer Delay Output Buffer Delay Clock to output from Address or Data with no output register Clock to output from EBR output Register Setup Data to EBR Memory Hold Data to EBR Memory Hold Address to EBR Memory Hold Write/Read Enable to EBR Memory Clock Enable Setup Time to EBR Output Register Clock Enable Hold Time to EBR Output Register Reset To Output Delay Time from EBR Output Register Reset Recovery to Rising Clock Reset Signal Setup Time -- -- -- 0.15 -0.07 0.18 -0.04 -- -- -- -- -0.25 0.39 -0.65 0.99 -0.30 0.47 -- -- 0.39 0.62 1.26 -- -- -- -- 0.56 0.74 0.77 0.56 -- -- -- -- -- -- 1.06 1.80 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Units
PFU Dual Port Memory Mode Timing
tSUADDR_PFU Address Setup Time tSUWREN_PFU Write/Read Enable Setup Time PIO Input/Output Buffer Timing
EBR Timing (1200 and 2280 Devices Only) tCO_EBR tCOO_EBR tSUDATA_EBR tHDATA_EBR tHADDR_EBR tHWREN_EBR tSUCE_EBR tHCE_EBR tRSTO_EBR -- -- -0.37 0.57 -0.37 0.57 -0.23 0.36 0.27 -0.18 -- 3.14 0.75 -- -- -- -- -- -- -- -- 1.44 ns ns ns ns ns ns ns ns ns ns ns
tSUADDR_EBR Setup Address to EBR Memory tSUWREN_EBR Setup Write/Read Enable to EBR Memory
PLL Parameters (1200 and 2280 Devices Only) tRSTREC tRSTSU -- 1.00 1.00 -- ns ns
1. Internal parameters are characterized but not tested on every device. Rev. A 0.19
3-14
Lattice Semiconductor
DC and Switching Characteristics LA-MachXO Automotive Family Data Sheet
LA-MachXO Family Timing Adders1, 2, 3 www..com
Over Recommended Operating Conditions
Buffer Type Input Adjusters LVDS254 BLVDS25 LVTTL33 LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 PCI33
4 4
Description LVDS BLVDS LVPECL LVTTL LVCMOS 3.3 LVCMOS 2.5 LVCMOS 1.8 LVCMOS 1.5 LVCMOS 1.2 PCI LVDS 2.5 E LVDS 2.5 BLVDS 2.5 LVPECL 3.3 LVTTL 4mA drive LVTTL 8mA drive LVTTL 12mA drive LVTTL 16mA drive LVCMOS 3.3 4mA drive LVCMOS 3.3 8mA drive LVCMOS 3.3 12mA drive LVCMOS 3.3 14mA drive LVCMOS 2.5 4mA drive LVCMOS 2.5 8mA drive LVCMOS 2.5 12mA drive LVCMOS 2.5 14mA drive LVCMOS 1.8 4mA drive LVCMOS 1.8 8mA drive LVCMOS 1.8 12mA drive LVCMOS 1.8 14mA drive LVCMOS 1.5 4mA drive LVCMOS 1.5 8mA drive LVCMOS 1.2 2mA drive LVCMOS 1.2 6mA drive PCI33
-3 0.61 0.61 0.59 0.01 0.01 0.00 0.10 0.19 0.56 0.01 -0.18 -0.30 -0.04 0.05 0.05 0.08 -0.01 0.70 0.05 0.08 -0.01 0.70 0.07 0.13 0.00 0.47 0.15 0.06 -0.08 0.09 0.22 0.07 0.36 0.07 2.59
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
LVPECL334
Output Adjusters LVDS25E LVDS254 BLVDS25 LVPECL33 LVTTL33_4mA LVTTL33_8mA LVTTL33_12mA LVTTL33_16mA LVCMOS33_4mA LVCMOS33_8mA LVCMOS33_12mA LVCMOS33_14mA LVCMOS25_4mA LVCMOS25_8mA LVCMOS25_12mA LVCMOS25_14mA LVCMOS18_4mA LVCMOS18_8mA LVCMOS18_12mA LVCMOS18_14mA LVCMOS15_4mA LVCMOS15_8mA LVCMOS12_2mA LVCMOS12_6mA PCI334
1. Timing adders are characterized but not tested on every device. 2. LVCMOS timing is measured with the load specified in Switching Test Conditions table. 3. All other standards tested according to the appropriate specifications. 4. I/O standard only available in LCMXO1200 and LCMXO2280 devices. Rev. A 0.19
3-15
Lattice Semiconductor
DC and Switching Characteristics LA-MachXO Automotive Family Data Sheet
sysCLOCK PLL Timing www..com
Over Recommended Operating Conditions
Parameter fIN fOUT fOUT2 fVCO fPFD tDT tPH
4
Descriptions Input Clock Frequency (CLKI, CLKFB) Output Clock Frequency (CLKOP, CLKOS) K-Divider Output Frequency (CLKOK) PLL VCO Frequency Phase Detector Input Frequency Output Clock Duty Cycle Output Phase Accuracy Output Clock Period Jitter Input Clock to Output Clock Skew Output Clock Pulse Width PLL Lock-in Time Programmable Delay Unit Input Clock Period Jitter External Feedback Delay Input Clock High Time Input Clock Low Time RST Pulse Width
Conditions
Min. 25 25 0.195 420 25
Max. 420 420 210 840 -- 55 0.05 +/-120 0.02 +/-200 -- 150 450 +/-200 10 -- -- --
Units MHz MHz MHz MHz MHz % UI ps UIPP ps ns s ps ps ns ns ns ns
AC Characteristics Default duty cycle selected3 Fout 100MHz Fout < 100MHz Divider ratio = integer At 90% or 10%3 45 -- -- -- -- 1 -- 100 -- -- 90% to 90% 10% to 10% 0.5 0.5 10
tOPJIT1 tSK tW tLOCK2 tPA tIPJIT tFBKDLY tHI tLO tRST
1. Jitter sample is taken over 10,000 samples of the primary PLL output with a clean reference clock. 2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment. 3. Using LVDS output buffers. 4. CLKOS as compared to CLKOP output. Rev. A 0.19
LA-MachXO "C" Sleep Mode Timing
Symbol tPWRDN tPWRUP tWSLEEPN tWAWAKE
Rev. A 0.19
Parameter SLEEPN Low to Power Down SLEEPN High to Power Up SLEEPN Pulse Width SLEEPN Pulse Rejection All
Device LCMXO256 LCMXO640 All All
Min. -- -- -- 400 --
Typ. -- -- -- -- --
Max 400 400 600 -- 100
Units ns s s ns ns
Power Down Mode I/O
tPWRUP tPWRDN
SLEEPN
tWSLEEPN or tWAWAKE
3-16
Lattice Semiconductor
DC and Switching Characteristics LA-MachXO Automotive Family Data Sheet
Flash Download Time www..com
Symbol Parameter LCMXO256 tREFRESH Minimum VCC or VCCAUX LCMXO640 (later of the two supplies) LCMXO1200 to Device I/O Active LCMXO2280 Min. -- -- -- -- Typ. -- -- -- -- Max. 0.4 0.6 0.8 1.0 Units ms ms ms ms
JTAG Port Timing Specifications
Over Recommended Operating Conditions
Symbol fMAX tBTCP tBTCPH tBTCPL tBTS tBTH tBTRF tBTCO tBTCODIS tBTCOEN tBTCRS tBTCRH tBUTCO tBTUODIS tBTUPOEN
Rev. A 0.19
Parameter TCK [BSCAN] clock frequency TCK [BSCAN] clock pulse width TCK [BSCAN] clock pulse width high TCK [BSCAN] clock pulse width low TCK [BSCAN] setup time TCK [BSCAN] hold time TCK [BSCAN] rise/fall time TAP controller falling edge of clock to output valid TAP controller falling edge of clock to output disabled TAP controller falling edge of clock to output enabled BSCAN test capture register setup time BSCAN test capture register hold time BSCAN test update register, falling edge of clock to output valid BSCAN test update register, falling edge of clock to output disabled BSCAN test update register, falling edge of clock to output enabled
Min. -- 40 20 20 8 10 50 -- -- -- 8 25 -- -- --
Max. 25 -- -- -- -- -- -- 10 10 10 -- -- 25 25 25
Units MHz ns ns ns ns ns mV/ns ns ns ns ns ns ns ns ns
Figure 3-5. JTAG Port Timing Waveforms
TMS
TDI tBTS tBTCPH TCK tBTCPL tBTH tBTCP
tBTCOEN TDO Valid Data
tBTCO Valid Data
tBTCODIS
tBTCRS Data to be captured from I/O tBTUPOEN Data to be driven out to I/O
tBTCRH Data Captured
tBUTCO Valid Data
tBTUODIS Valid Data
3-17
Lattice Semiconductor
DC and Switching Characteristics LA-MachXO Automotive Family Data Sheet
Switching Test Conditions www..com
Figure 3-6 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Figure 3-5. Figure 3-6. Output Test Load, LVTTL and LVCMOS Standards
VT R1 DUT CL Test Poi nt
Table 3-5. Test Fixture Required Components, Non-Terminated Interfaces
Test Condition R1 CL Timing Ref. LVTTL, LVCMOS 3.3 = 1.5V LVCMOS 2.5 = VCCIO/2 LVTTL and LVCMOS settings (L -> H, H -> L) VT -- -- -- -- -- VOL VOH VOL VOH VOL VOH
0pF
LVCMOS 1.8 = VCCIO/2 LVCMOS 1.5 = VCCIO/2 LVCMOS 1.2 = VCCIO/2
LVTTL and LVCMOS 3.3 (Z -> H) LVTTL and LVCMOS 3.3 (Z -> L) Other LVCMOS (Z -> H) Other LVCMOS (Z -> L) LVTTL + LVCMOS (H -> Z) LVTTL + LVCMOS (L -> Z) 188 0pF
1.5 VCCIO/2 VCCIO/2 VOH - 0.15 VOL - 0.15
Note: Output test conditions for all other interfaces are determined by the respective standards.
3-18
www..com
LA-MachXO Automotive Family Data Sheet Pinout Information
Data Sheet DS1003
November 2007
Signal Descriptions
Signal Name General Purpose [Edge] indicates the edge of the device on which the pad is located. Valid edge designations are L (Left), B (Bottom), R (Right), T (Top). [Row/Column Number] indicates the PFU row or the column of the device on which the PIO Group exists. When Edge is T (Top) or (Bottom), only need to specify Row Number. When Edge is L (Left) or R (Right), only need to specify Column Number. P[Edge] [Row/Column Number]_[A/B/C/D/E/F] I/O [A/B/C/D/E/F] indicates the PIO within the group to which the pad is connected. Some of these user programmable pins are shared with special function pins. When not used as special function pins, these pins can be programmed as I/Os for user logic. During configuration of the user-programmable I/Os, the user has an option to tri-state the I/Os and enable an internal pull-up resistor. This option also applies to unused pins (or those not bonded to a package pin). The default during configuration is for user-programmable I/Os to be tri-stated with an internal pull-up resistor enabled. GSRN TSALL NC GND VCC VCCAUX VCCIOx SLEEPN1 I I -- -- -- -- -- I Global RESET signal (active low). Dedicated pad, when not in use it can be used as an I/O pin. TSALL is a dedicated pad for the global output enable signal. When TSALL is high all the outputs are tristated. It is a dual function pin. When not in use, it can be used as an I/O pin. No connect. GND - Ground. Dedicated pins. VCC - The power supply pins for core logic. Dedicated pins. VCCAUX - the Auxiliary power supply pin. This pin powers up a variety of internal circuits including all the differential and referenced input buffers. Dedicated pins. VCCIO - The power supply pins for I/O Bank x. Dedicated pins. Sleep Mode pin - Active low sleep pin. When this pin is held high, the device operates normally. This pin has a weak internal pull-up, but when unused, an external pull-up to VCC is recommended. When driven low, the device moves into Sleep mode after a specified time. Reference clock (PLL) input Pads: [LOC] indicates location. Valid designations are ULM (Upper PLL) and LLM (Lower PLL). T = true and C = complement. Optional feedback (PLL) input Pads: [LOC] indicates location. Valid designations are ULM (Upper PLL) and LLM (Lower PLL). T = true and C = complement. Primary Clock Pads, n per side. Test Mode Select input pin, used to control the 1149.1 state machine. Test Clock input pin, used to clock the 1149.1 state machine. Test Data input pin, used to load data into the device using an 1149.1 state machine. Output pin -Test Data output pin used to shift data out of the device using 1149.1. I/O Descriptions
PLL and Clock Functions (Used as user programmable I/O pins when not used for PLL or clock pins) [LOC][0]_PLL[T, C]_IN [LOC][0]_PLL[T, C]_FB PCLK [n]_[1:0] TMS TCK TDI TDO -- -- -- I I I O
Test and Programming (Dedicated pins)
1. Applies to LA-MachXO "C" devices only. NC for "E" devices.
(c) 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
4-1
DS1003 Pinouts_01.3
Lattice Semiconductor
Pinout Information LA-MachXO Automotive Family Data Sheet
Pin Information Summary www..com
LAMXO256C/E Pin Type Single Ended User I/O Differential Pair User I/O1 Muxed TAP Dedicated (Total Without Supplies) VCC VCCAUX Bank0 VCCIO Bank1 Bank2 Bank3 GND NC Bank0 Single Ended/Differential I/O per Bank Bank1 Bank2 Bank3 100 TQFP 78 38 6 4 5 2 1 3 3 -- -- 8 0 41/20 37/18 -- -- 100 TQFP 74 17 6 4 5 2 1 2 2 2 2 10 0 18/5 21/4 14/2 21/6 LAMXO640C/E 144 TQFP 113 43 6 4 5 4 2 2 2 2 2 12 0 29/10 30/11 24/9 30/13 256 ftBGA 159 79 6 4 5 4 2 4 4 4 4 18 52 42/21 40/20 36/18 40/20
1. These devices support emulated LVDS outputs. LVDS inputs are not supported.
LAMXO1200E Pin Type Single Ended User I/O Differential Pair User I/O Muxed TAP Dedicated (Total Without Supplies) VCC VCCAUX Bank0 Bank1 Bank2 VCCIO Bank3 Bank4 Bank5 Bank6 Bank7 GND NC Bank0 Bank1 Bank2 Single Ended/Differential I/O Bank3 per Bank Bank4 Bank5 Bank6 Bank7
1
LAMXO2280E 256 ftBGA 211 105 6 4 5 4 2 2 2 2 2 2 2 2 2 18 0 26/13 28/14 26/13 28/14 27/13 22/11 28/14 26/13 100 TQFP 73 30 6 4 5 2 2 1 1 1 1 1 1 1 1 8 0 9/3 9/3 10/4 11/5 8/3 5/2 10/4 11/5 144 TQFP 113 47 6 4 5 4 2 1 1 1 1 1 1 1 1 12 0 13/6 16/7 15/7 15/7 14/4 10/4 15/6 15/6 256 ftBGA 211 105 6 4 5 4 2 2 2 2 2 2 2 2 2 18 0 24/12 30/15 26/13 28/14 29/14 20/10 28/14 26/13 324 ftBGA 271 134 6 4 5 6 2 2 2 2 2 2 2 2 2 24 0 34/17 36/18 34/17 34/17 35/17 30/15 34/17 34/17
100 TQFP 73 27 6 4 5 4 2 1 1 1 1 1 1 1 1 8 0 10/3 8/2 10/4 11/5 8/3 5/2 10/3 11/5
144 TQFP 113 48 6 4 5 4 2 1 1 1 1 1 1 1 1 12 0 14/6 15/7 15/7 15/7 14/5 10/4 15/6 15/6
1. These devices support on-chip LVDS buffers for left and right I/O Banks.
4-2
Lattice Semiconductor
Pinout Information LA-MachXO Automotive Family Data Sheet
Power Supply and NC www..com
Signal VCC VCCIO0 100 TQFP1 LAMXO256/640: 35, 90 LAMXO1200/2280: 17, 35, 66, 91 LAMXO256: 60, 74, 92 LAMXO640: 80, 92 LAMXO1200/2280: 94 LAMXO256: 10, 24, 41 LAMXO640: 60, 74 LAMXO1200/2280: 80 LAMXO256: None LAMXO640: 29, 41 LAMXO1200/2280: 70 LAMXO256: None LAMXO640: 10, 24 LAMXO1200/2280: 56 LAMXO256/640: None LAMXO1200/2280: 44 LAMXO256/640: None LAMXO1200/2280: 27 LAMXO256/640: None LAMXO1200/2280: 20 LAMXO256/640: None LAMXO1200/2280: 6 LAMXO256/640: 88 LAMXO1200/2280: 36, 90 LAMXO256: 40, 84, 62, 75, 93, 12, 25, 42 LAMXO640: 40, 84, 81, 93, 62, 75, 30, 42, 12, 25 LAMXO1200/2280: 9, 41, 59, 83, 100, 76, 50, 26 21, 52, 93, 129 LAMXO640: 117, 135 LAMXO1200/2280: 135 LAMXO640: 82, 98 LAMXO1200/2280: 117 LAMXO640: 38, 63 LAMXO1200/2280: 98 LAMXO640: 10, 26 LAMXO1200/2280: 82 LAMXO640: None LAMXO1200/2280: 63 LAMXO640: None LAMXO1200/2280: 38 LAMXO640: None LAMXO1200/2280: 26 LAMXO640: None LAMXO1200/2280: 10 53, 128 16, 59, 88, 123, 118, 136, 83, 99, 37, 64, 11, 27 144 TQFP1
VCCIO1
VCCIO2
VCCIO3
VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCAUX GND2
NC3
1. Pin orientation follows the conventional order from pin 1 marking of the top side view and counter-clockwise. 2. All grounds must be electrically connected at the board level. For fpBGA and ftBGA packages, the total number of GND balls is less than the actual number of GND logic connections from the die to the common package GND plane. 3. NC pins should not be connected to any active signals, VCC or GND.
4-3
Lattice Semiconductor
Pinout Information LA-MachXO Automotive Family Data Sheet
Power Supply and NC (Cont.) www..com
Signal VCC VCCIO0 VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCAUX GND2 G7, G10, K7, K10 LAMXO640: F8, F7, F9, F10 LAMXO1200/2280: F8, F7 LAMXO640: H11, G11, K11, J11 LAMXO1200/2280: F9, F10 LAMXO640: L9, L10, L8, L7 LAMXO1200/2280: H11, G11 LAMXO640: K6, J6, H6, G6 LAMXO1200/2280: K11, J11 LAMXO640: None LAMXO1200/2280: L9, L10 LAMXO640: None LAMXO1200/2280: L8, L7 LAMXO640: None LAMXO1200/2280: K6, J6 LAMXO640: None LAMXO1200/2280: H6, G6 T9, A8 A1, A16, F11, G8, G9, H7, H8, H9, H10, J7, J8, J9, J10, K8, K9, L6, T1, T16 256 ftBGA1 G8, G7 G12, G10 J12, H12 L12, K12 M12, M11 M8, R9 M7, K7 H6, J7 M10, F9 E14, F16, H10, H11, H8, H9, J10, J11, J4, J8, J9, K10, K11, K17, K8, K9, L10, L11, L8, L9, N2, P14, P5, R7 324 ftBGA1 F14, G11, G9, H7, L7, M9
NC3
LAMXO640: E4, E5, F5, F6, C3, C2, G4, G5, H4, H5, -- K5, K4, M5, M4, P2, P3, N5, N6, M7, M8, N10, N11, R15, R16, P15, P16, M11, L11, N12, N13, M13, M12, K12, J12, F12, F13, E12, E13, D13, D14, B15, A15, C14, B14, E11, E10, E7, E6, D4, D3, B3, B2 LAMXO1200: None LAMXO2280: None
1. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order ascending horizontally. 2. All grounds must be electrically connected at the board level. For fpBGA and ftBGA packages, the total number of GND balls is less than the actual number of GND logic connections from the die to the common package GND plane. 3. NC pins should not be connected to any active signals, VCC or GND.
4-4
Lattice Semiconductor
Pinout Information LA-MachXO Automotive Family Data Sheet
www..com LA-MachXO256 and LA-MachXO640 Logic Signal Connections: 100 TQFP
LAMXO256 Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Ball Function PL2A PL2B PL3A PL3B PL3C PL3D PL4A PL4B PL5A VCCIO1 PL5B GNDIO1 PL5C PL5D PL6A PL6B PL7A PL7B PL7C PL7D PL8A PL8B PL9A VCCIO1 GNDIO1 TMS PL9B TCK PB2A PB2B TDO PB2C TDI PB2D VCC PB3A PB3B PB3C PB3D GND VCCIO1 Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PCLK1_0** PCLK1_1** T C T C TDI C TDO T TCK T C TMS C TSALL GSRN T C T C T C T C T C T C Dual Function Differential T C T C T C T C T Ball Function PL2A PL2C PL2B PL2D PL3A PL3B PL3C PL3D PL4A VCCIO3 PL4C GNDIO3 PL4D PL5B PL7B PL8C PL8D PL9A PL9C PL10A PL10C PL11A PL11C VCCIO3 GNDIO3 TMS PB2C TCK VCCIO2 GNDIO2 TDO PB4C TDI PB4E VCC PB5B PB5D PB6B PB6C GND VCCIO2
LAMXO640 Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 PCLK2_0** PCLK2_1** TDI TDO TCK TMS TSALL T C GSRN C T Dual Function Differential T T C C T C T C
4-5
Lattice Semiconductor
Pinout Information LA-MachXO Automotive Family Data Sheet
LA-MachXO256 and LA-MachXO640 Logic Signal Connections: www..com 100 TQFP (Cont.)
LAMXO256 Pin Number 42 43 44 45 46 47 48* 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 Ball Function GNDIO1 PB4A PB4B PB4C PB4D PB5A SLEEPN PB5C PB5D PR9B PR9A PR8B PR8A PR7D PR7C PR7B PR7A PR6B VCCIO0 PR6A GNDIO0 PR5D PR5C PR5B PR5A PR4B PR4A PR3D PR3C PR3B PR3A PR2B VCCIO0 GNDIO0 PR2A PT5C PT5B PT5A PT4F PT4E PT4D Bank 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C T C T C T C T C T C T C T C T C T SLEEPN T C C T C T C T C T C T C T C Dual Function Differential Ball Function GNDIO2 PB8B PB8C PB8D PB9A PB9C SLEEPN PB9D PB9F PR11D PR11B PR11C PR11A PR10D PR10C PR10B PR10A PR9D VCCIO1 PR9B GNDIO1 PR7B PR6C PR6B PR5D PR5B PR4D PR4B PR3D PR3B PR2D PR2B VCCIO1 GNDIO1 PT9F PT9E PT9C PT9A VCCIO0 GNDIO0 PT7E LAMXO640 Bank 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 C T C C T T C T C T SLEEPN C T T C Dual Function Differential
4-6
Lattice Semiconductor
Pinout Information LA-MachXO Automotive Family Data Sheet
LA-MachXO256 and LA-MachXO640 Logic Signal Connections: www..com 100 TQFP (Cont.)
LAMXO256 Pin Number 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Ball Function PT4C GND PT4B PT4A PT3D VCCAUX PT3C VCC PT3B VCCIO0 GNDIO0 PT3A PT2F PT2E PT2D PT2C PT2B PT2A Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T C T C T C T C T PCLK0_1** PCLK0_0** C T C Dual Function Differential T Ball Function PT7A GND PT6B PT5B PT5A VCCAUX PT4F VCC PT3F VCCIO0 GNDIO0 PT3B PT3A PT2F PT2E PT2B PT2C PT2A LAMXO640 Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T C T C T C PCLK0_1** PCLK0_0** C T Dual Function Differential
* NC for "E" devices. ** Primary clock inputs are single-ended.
4-7
Lattice Semiconductor
Pinout Information LA-MachXO Automotive Family Data Sheet
www..com LA-MachXO1200 and LA-MachXO2280 Logic Signal Connections: 100 TQFP
LAMXO1200 Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26** 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Ball Function PL2A PL2B PL3C PL3D PL4B VCCIO7 PL6A PL6B GND PL7C PL7D PL8C PL8D PL9C PL10A PL10B VCC PL11B PL11C VCCIO6 PL13C PL14A PL14B PL15A PL15B GNDIO6 GNDIO5 VCCIO5 TMS TCK PB3B PB4A PB4B TDO TDI VCC VCCAUX PB6E PB6F PB7B PB7F Bank 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 PCLK4_1*** PCLK4_0*** T C TDO TDI T C TMS TCK LLM0_PLLT_FB_A LLM0_PLLC_FB_A LLM0_PLLT_IN_A LLM0_PLLC_IN_A T* C* T* C* TSALL T* C* T C T C GSRN T* C* Dual Function Differential T C T C Ball Function PL2A PL2B PL3C PL3D PL4B VCCIO7 PL7A PL7B GND PL9C PL9D PL10C PL10D PL11C PL13A PL13B VCC PL14D PL14C VCCIO6 PL16C PL17A PL17B PL18A PL18B GNDIO6 GNDIO5 VCCIO5 TMS TCK PB3B PB4A PB4B TDO TDI VCC VCCAUX PB8E PB8F PB10F PB10B Bank 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4
LAMXO2280 Dual Function LUM0_PLLT_FB_A LUM0_PLLC_FB_A LUM0_PLLT_IN_A LUM0_PLLC_IN_A Differential T C T C
T* GSRN C* T C T C T* C* C TSALL T
LLM0_PLLT_FB_A LLM0_PLLC_FB_A LLM0_PLLT_IN_A LLM0_PLLC_IN_A
T* C* T* C*
TMS TCK T C TDO TDI
T C PCLK4_1*** PCLK4_0***
4-8
Lattice Semiconductor
Pinout Information LA-MachXO Automotive Family Data Sheet
LA-MachXO1200 and LA-MachXO2280 Logic Signal Connections: www..com 100 TQFP (Cont.)
LAMXO1200 Pin Number 41 42 43 44 45 46 47 48 49 50** 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76** 77 78 79 Ball Function GND PB9A PB9B VCCIO4 PB10A PB10B NC PB11A PB11B GNDIO3 GNDIO4 PR16B PR15B PR15A PR14B PR14A VCCIO3 PR12B PR12A GND PR10B PR10A PR9B PR9A PR8B PR8A VCC PR6C PR6B PR6A VCCIO2 PR4D PR4B PR4A PR2B PR2A GNDIO1 GNDIO2 PT11C PT11B PT11A Bank 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 1 1 1 C T C* T* C T C* T* C* T* C* T* C* T* C* T* C* T* C* T* NC T C T C T C Dual Function Differential Ball Function GND PB12A PB12B VCCIO4 PB13A PB13B NC PB16A PB16B GNDIO3 GNDIO4 PR19B PR18B PR18A PR17B PR17A VCCIO3 PR15B PR15A GND PR13B PR13A PR11B PR11A PR10B PR10A VCC PR8C PR8B PR8A VCCIO2 PR5D PR5B PR5A PR3B PR3A GNDIO1 GNDIO2 PT15C PT14B PT14A Bank 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 1 1 1 C T C* T* C* T* C* T* C* T* C* T* C* T* C* T* C* T* C* T* NC T C T C T C LAMXO2280 Dual Function Differential
4-9
Lattice Semiconductor
Pinout Information LA-MachXO Automotive Family Data Sheet
LA-MachXO1200 and LA-MachXO2280 Logic Signal Connections: www..com 100 TQFP (Cont.)
LAMXO1200 Pin Number 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100** Ball Function VCCIO1 PT9E PT9A GND PT8B PT8A PT7D PT6F PT6D PT6C VCCAUX VCC PT5B PT4B VCCIO0 PT3D PT3C PT3B PT2B PT2A GNDIO0 GNDIO7 Bank 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 C T C T PCLK1_1*** PCLK1_0*** C T C T Dual Function Differential Ball Function VCCIO1 PT12D PT12C GND PT11B PT11A PT10B PT9B PT8F PT8E VCCAUX VCC PT6D PT6F VCCIO0 PT4B PT4A PT3B PT2B PT2A GNDIO0 GNDIO7 Bank 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 C T C T PCLK1_1*** PCLK1_0*** C T C T C T LAMXO2280 Dual Function Differential
*Supports true LVDS outputs. **Double bonded to the pin. *** Primary clock inputs are single-ended.
4-10
Lattice Semiconductor
Pinout Information LA-MachXO Automotive Family Data Sheet
www..com LA-MachXO640, LA-MachXO1200 and LA-MachXO2280 Logic Signal Connections: 144 TQFP
LAMXO640 Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
LAMXO1200 Differential
T T C T C C T C
LAMXO2280 Differential
T C T* C* T C T* C*
Ball Function
PL2A PL2C PL2B PL3A PL2D PL3B PL3C PL3D PL4A VCCIO3 GNDIO3 PL4D PL5A PL5B PL5D GND PL6C PL6D PL7A PL7B VCC PL8A PL8B PL8C PL9C VCCIO3 GNDIO3 PL9D PL10A PL10B PL10C PL11A PL10D PL11C PL11B PL11D GNDIO2 VCCIO2 TMS PB2C PB3A TCK PB3B PB3C PB3D PB4A TDO PB4B PB4C PB4D
Bank
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Dual Function
Ball Function
PL2A PL2B PL3A PL3B PL3C PL3D PL4A PL4B PL4C VCCIO7 GNDIO7 PL5C
Bank
7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5
Dual Function
Ball Function
PL2A PL2B PL3A PL3B PL3C PL3D PL4A PL4B PL4C VCCIO7 GNDIO7 PL6C
Bank
7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5
Dual Function
LUM0_PLLT_FB_A LUM0_PLLC_FB_A
Differential
T C T* C*
LUM0_PLLT_IN_A LUM0_PLLC_IN_A
T C T* C*
T GSRN C
PL6A PL6B PL6D GND
T* GSRN C*
PL7A PL7B PL7D GND
T* GSRN C*
T C T C
PL7C PL7D PL10A PL10B VCC
T C T* C*
PL9C PL9D PL13A PL13B VCC
T C T* C*
T C TSALL T
PL11A PL11B PL11C PL12B VCCIO6 GNDIO6
T* C* TSALL
PL13D PL14D PL14C PL15B VCCIO6 GNDIO6 PL16D
C TSALL T
C T C T T C T C C
PL13D PL14A PL14B PL14C PL14D PL15A PL15B PL16A PL16B GNDIO5 VCCIO5
LLM0_PLLT_FB_A LLM0_PLLC_FB_A
T* C* T C
PL17A PL17B PL17C PL17D PL18A PL18B PL19A PL19B GNDIO5 VCCIO5
LLM0_PLLT_FB_A LLM0_PLLC_FB_A
T* C* T C
LLM0_PLLT_IN_A LLM0_PLLC_IN_A
T* C* T C
LLM0_PLLT_IN_A LLM0_PLLC_IN_A
T* C* T C
TMS
TMS PB2C T PB2D TCK C T C T PB3A PB3B PB4A PB4B TDO C T C PB4D PB5A PB5B
TMS T C TCK T C T C TDO
TMS PB2A PB2B TCK PB3A PB3B PB4A PB4B TDO PB4D T C PB5A PB5B
TMS T C TCK T C T C TDO
TCK
TDO
T C
4-11
Lattice Semiconductor
Pinout Information LA-MachXO Automotive Family Data Sheet
LA-MachXO640, LA-MachXO1200 and LA-MachXO2280 Logic Signal www..com Connections: 144 TQFP (Cont.)
LAMXO640 Pin Number
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70** 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
LAMXO1200 Differential Ball Function
TDI VCC VCCAUX T PB6F PB7B PB7C T PB7D PB7F GND PB9A PB9B PB9E VCCIO4 GNDIO4 T C T T C PB10A PB10B PB10C PB10D PB10F NC C PB11C PB11D C C T C T C T T PR16B PR16A PR15B PR15A PR14D PR14C PR14B PR14A PR13D VCCIO3 GNDIO3 PR12B PR12A PR11B PR11A GND C T C T PR10B PR10A PR8B PR8A VCC PR6B PR6A PR5B C PR5A VCCIO2 GNDIO2 T PR4C
LAMXO2280 Differential Ball Function
TDI VCC VCCAUX PB8F
Ball Function
TDI VCC VCCAUX PB5A PB5B PB5D PB6A PB6B GND PB7C PB7E PB8A VCCIO2 GNDIO2 PB8C PB8D PB9A PB9C PB9B SLEEPN PB9D PB9F PR11D PR11B PR11C PR10D PR11A PR10B PR10C PR10A PR9D VCCIO1 GNDIO1 PR9A PR8C PR8A PR7D GND PR7B PR7A PR6D PR6C VCC PR5D PR5B PR4D PR4B VCCIO1 GNDIO1 PR4A
Bank
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Dual Function
TDI
Bank
5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2
Dual Function
TDI
Bank
5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2
Dual Function
TDI
Differential
PCLKT2_1***
C
PCLK4_1*** T C PCLK4_0***
PB10F PB10C PB10D PB10B GND T C PB12A PB12B PB12E VCCIO4 GNDIO4 T C T C PB13A PB13B PB13C PB13D PB14D NC T C C T C* T* C T C* T* PB16C PB16D PR20B PR20A PR19B PR19A PR17D PR17C PR17B PR17A PR16D VCCIO3 GNDIO3 C* T* C* T* PR15B PR15A PR14B PR14A GND C* T* C* T* PR13B PR13A PR10B PR10A VCC C* T* C* T* PR8B PR8A PR7B PR7A VCCIO2 GNDIO2 PR5C
PCLK4_1*** T C PCLK4_0***
PCLKT2_0***
C
T C
T C T C
SLEEPN
T C C T C T C T C* T*
C* T* C* T*
C* T* C* T*
C* T* C* T*
4-12
Lattice Semiconductor
Pinout Information LA-MachXO Automotive Family Data Sheet
LA-MachXO640, LA-MachXO1200 and LA-MachXO2280 Logic Signal www..com Connections: 144 TQFP (Cont.)
LAMXO640 Pin Number
101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
LAMXO1200 Differential
C T C C T C T T C C T C T T
LAMXO2280 Differential
C* T* C T C* T* C T C T C T C T C T
Ball Function
PR3D PR3C PR3B PR2D PR3A PR2B PR2C PR2A PT9F PT9D PT9E PT9B PT9C PT9A PT8C PT8B VCCIO0 GNDIO0 PT8A PT7E PT7C PT7A GND PT6B PT6A PT5C PT5B VCCAUX VCC PT4D PT4B PT4A PT3F PT3D VCCIO0 GNDIO0 PT3B PT2F PT3A PT2D PT2E PT2B PT2C PT2A
Bank
1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Dual Function
Ball Function
PR4B PR4A PR3D PR3C PR3B PR3A PR2B PR2A PT11D PT11C PT11B PT11A PT10F PT10E PT10D
Bank
2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Dual Function
Ball Function
PR5B PR5A PR4D PR4C PR4B PR4A PR3B PR3A PT16D PT16C PT16B PT16A PT15D PT15C PT14B PT14A VCCIO1 GNDIO1
Bank
2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Dual Function
Differential
C* T* C T C* T* C* T* C T C T C T C T
C
PT10C VCCIO1 GNDIO1
T
PT9F PT9E PT9B PT9A GND
C T C T
PT12F PT12E PT12D PT12C GND
C T C T
PCLK0_1***
C T
PT7D PT7B PT7A
PCLK1_1*** C T PCLK1_0***
PT10B PT9D PT9C PT9B VCCAUX VCC C T C T PT7B PT7A PT6D PT6E PT6F VCCIO0 GNDIO0 C T C T C T C T PT4B PT4A PT3B PT3A PT2D PT2C PT2B PT2A
PCLK1_1*** C T PCLK1_0***
PCLK0_0***
PT6F VCCAUX VCC PT5D C T PT5C PT5B PT5A PT4B VCCIO0 GNDIO0 C C T C T C T T PT3D PT3C PT3B PT3A PT2D PT2C PT2B PT2A
C T
T C
T C C T C T C T
*Supports true LVDS outputs. **NC for "E" devices. ***Primary clock inputs arer single-ended.
4-13
Lattice Semiconductor
Pinout Information LA-MachXO Automotive Family Data Sheet
www..com LA-MachXO640, LA-MachXO1200 and LA-MachXO2280 Logic Signal Connections: 256 ftBGA
LAMXO640 Ball Ball Number Function Bank
GND VCCIO3 E4 E5 F5 F6 F3 F4 E3 E2 C3 C2 B1 C1 VCCIO3 GND D2 D1 F2 G2 E1 F1 G4 G5 GND G3 H3 H4 H5 G1 H1 H2 J2 J3 K3 J1 K1 K2 L2 L1 M1 P1 N1 L3 M3 M2 N2 VCCIO3 GND GNDIO3 VCCIO3 NC NC NC NC PL3A PL3B PL2C PL2D NC NC PL2A PL2B VCCIO3 GNDIO3 PL3C PL3D PL5A PL5B PL4A PL4B NC NC GND PL4C PL4D NC NC PL5C PL5D PL6A PL6B PL7C PL7D PL6C PL6D PL9A PL9B PL7A PL7B PL8D PL8C PL10A PL10B PL9C PL9D VCCIO3 GNDIO3 3 3 3 3 3 3 3 3 3 3 3 3 3 TSALL C T C T C C T T C T C 3 3 3 3 3 3 3 T C T C T C T 3 3 T C 3 3 3 3 3 3 3 3 3 3 GSRN T C T C T C T C 3 3 3 3 T C T C 3 3
LAMXO1200 Ball Ball Differential Number Function Bank
GND VCCIO7 E4 E5 F5 F6 F3 F4 E3 E2 C3 C2 B1 C1 VCCIO7 GND D2 D1 F2 G2 E1 F1 G4 G5 GND G3 H3 H4 H5 VCCIO7 GND G1 H1 H2 J2 J3 K3 J1 VCCIO6 GND K1 K2 L2 L1 M1 P1 N1 L3 M3 M2 N2 VCCIO6 GND GNDIO7 VCCIO7 PL2A PL2B PL3A PL3B PL3C PL3D PL4A PL4B PL4C PL4D PL5A PL5B VCCIO7 GNDIO7 PL5C PL5D PL6A PL6B PL6C PL6D PL7A PL7B GND PL7C PL7D PL8A PL8B VCCIO7 GNDIO7 PL8C PL8D PL9A PL9B PL9C PL9D PL10A VCCIO6 GNDIO6 PL10B PL10C PL10D PL11A PL11B PL11D PL11C PL12A PL12B PL12C PL12D VCCIO6 GNDIO6 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 TSALL C** T C T** C** C T T** C** T C T C T** C** T C T** T C T** C** GSRN T C T** C** T C T** C** T C T** C** T C T** C** T C T** C**
LAMXO2280 Ball Ball Differential Number Function Bank
GND VCCIO7 E4 E5 F5 F6 F3 F4 E3 E2 C3 C2 B1 C1 VCCIO7 GND D2 D1 F2 G2 E1 F1 G4 G5 GND G3 H3 H4 H5 VCCIO7 GND G1 H1 H2 J2 J3 K3 J1 VCCIO6 GND K1 K2 L2 L1 M1 P1 N1 L3 M3 M2 N2 VCCIO6 GND GNDIO7 VCCIO7 PL2A PL2B PL3A PL3B PL3C PL3D PL4A PL4B PL4C PL4D PL5A PL5B VCCIO7 GNDIO7 PL6C PL6D PL7A PL7B PL7C PL7D PL8A PL8B GND PL8C PL8D PL9A PL9B VCCIO7 GNDIO7 PL10C PL10D PL11A PL11B PL11C PL11D PL12A VCCIO6 GNDIO6 PL12B PL12C PL12D PL13A PL13B PL14D PL14C PL15A PL15B PL15C PL15D VCCIO6 GNDIO6 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 TSALL C** T C T** C** C T T** C** T C T C T** C** T C T** T C T** C** GSRN T C T** C** T C T** C** LUM0_PLLT_IN_A LUM0_PLLC_IN_A LUM0_PLLT_FB_A LUM0_PLLC_FB_A T C T** C** T C T** C** T C T** C**
Dual Function
Dual Function
Dual Function
Differential
4-14
Lattice Semiconductor
Pinout Information LA-MachXO Automotive Family Data Sheet
LA-MachXO640, LA-MachXO1200 and LA-MachXO2280 Logic Signal www..com Connections: 256 ftBGA (Cont.)
LAMXO640 Ball Ball Number Function Bank
J4 J5 R1 R2 K5 K4 L5 L4 M5 M4 N4 N3 VCCIO3 GND GND VCCIO2 P4 P2 P3 N5 R3 N6 T2 T3 R4 R5 P5 P6 T5 M6 T4 R6 GND VCCIO2 T6 N7 T8 T7 M7 M8 T9 R7 R8 P7 P8 N8 N9 P10 P9 M9 PL8A PL8B PL11A PL11B NC NC PL10C PL10D NC NC PL11C PL11D VCCIO3 GNDIO3 GNDIO2 VCCIO2 TMS NC NC NC TCK NC PB2A PB2B PB2C PB2D PB3A PB3B PB3C TDO PB3D PB4A GNDIO2 VCCIO2 PB4B TDI PB4C PB4D NC NC VCCAUX PB4E PB4F PB5C PB5D PB5A PB5B PB7B PB7A PB6B 2 2 2 2 2 2 2 PCLK2_0**** PCLK2_1**** T C T C C T C 2 2 T C 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 TDI T C C TDO C T T C T C T C T 2 TCK 3 3 3 3 2 2 2 TMS T C 3 3 T C 3 3 3 3 -
LAMXO1200 Ball Ball Differential Number Function Bank
T C T C J4 J5 R1 R2 K5 K4 L5 L4 M5 M4 N4 N3 VCCIO6 GND GND VCCIO5 P4 P2 P3 N5 R3 N6 T2 T3 R4 R5 P5 P6 T5 M6 T4 R6 GND VCCIO5 T6 N7 T8 T7 M7 M8 T9 R7 R8 VCCIO5 GND P7 P8 N8 N9 P10 P9 M9 PL13A PL13B PL13C PL13D PL14A PL14B PL14C PL14D PL15A PL15B PL16A PL16B VCCIO6 GNDIO6 GNDIO5 VCCIO5 TMS PB2A PB2B PB2C TCK PB2D PB3A PB3B PB3C PB3D PB4A PB4B PB4C TDO PB4D PB5A GNDIO5 VCCIO5 PB5B TDI PB5C PB5D PB6A PB6B VCCAUX PB6C PB6D VCCIO5 GNDIO5 PB6E PB6F PB7A PB7B PB7D PB7C PB7F 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 PCLK4_0**** PCLK4_1**** T C T C C T C T C TDI T C T C C TDO C T TCK C T C T C T C T TMS T C T LLM0_PLLT_IN_A LLM0_PLLC_IN_A LLM0_PLLT_FB_A LLM0_PLLC_FB_A T** C** T C T** C** T C
LAMXO2280 Ball Ball Differential Number Function Bank
T** C** T C J4 J5 R1 R2 GND K5 K4 L5 L4 M5 M4 N4 N3 VCCIO6 GND GND VCCIO5 P4 P2 P3 N5 R3 N6 T2 T3 R4 R5 P5 P6 T5 M6 T4 R6 GND VCCIO5 T6 N7 T8 T7 M7 M8 T9 R7 R8 VCCIO5 GND P7 P8 N8 N9 P10 P9 M9 PL16A PL16B PL16C PL16D GND PL17A PL17B PL17C PL17D PL18A PL18B PL19A PL19B VCCIO6 GNDIO6 GNDIO5 VCCIO5 TMS PB2A PB2B PB2C TCK PB2D PB3A PB3B PB3C PB3D PB4A PB4B PB4C TDO PB4D PB5A GNDIO5 VCCIO5 PB5B TDI PB6A PB6B PB7C PB7D VCCAUX PB8C PB8D VCCIO5 GNDIO5 PB9A PB9B PB10E PB10F PB10D PB10C PB10B 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 PCLK4_0**** PCLK4_1**** T C T C C T C T C TDI T C T C C TDO C T TCK C T C T C T C T TMS T C T LLM0_PLLT_IN_A LLM0_PLLC_IN_A LLM0_PLLT_FB_A LLM0_PLLC_FB_A T** C** T C T** C** T C
Dual Function
Dual Function
Dual Function
Differential
T** C** T C
4-15
Lattice Semiconductor
Pinout Information LA-MachXO Automotive Family Data Sheet
LA-MachXO640, LA-MachXO1200 and LA-MachXO2280 Logic Signal www..com Connections: 256 ftBGA (Cont.)
LAMXO640 Ball Ball Number Function Bank
M10 R9 R10 T10 T11 N10 N11 VCCIO2 GND R11 R12 P11 P12 T13 T12 R13 R14 GND T14 T15 P13*** P14 R15 R16 P15 P16 VCCIO2 GND GND VCCIO1 M11 L11 N12 N13 M13 M12 N14 N15 L13 L12 M14 VCCIO1 GND L14 N16 M16 M15 L15 L16 K16 K13 PB6A PB6C PB6D PB7C PB7D NC NC VCCIO2 GNDIO2 PB7E PB7F PB8A PB8B PB8C PB8D PB9A PB9B GND PB9C PB9D SLEEPN PB9F NC NC NC NC VCCIO2 GNDIO2 GNDIO1 VCCIO1 NC NC NC NC NC NC PR11D PR11C PR11B PR11A PR10B VCCIO1 GNDIO1 PR10A PR10D PR10C PR9D PR9C PR9B PR9A PR8D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T C T C T C T C C T C T C 2 2 1 1 2 2 2 2 2 2 2 2 2 2 2 2 SLEEPN T C T C T C T C T C 2 2 2 2 2 T T C T C
LAMXO1200 Ball Ball Differential Number Function Bank
VCCIO4 GND M10 R9 R10 T10 T11 N10 N11 VCCIO4 GND R11 R12 P11 P12 T13 T12 R13 R14 GND T14 T15 P13 P14 R15 R16 P15 P16 VCCIO4 GND GND VCCIO3 M11 L11 N12 N13 M13 M12 N14 N15 L13 L12 M14 VCCIO3 GND L14 N16 M16 M15 L15 L16 K16 K13 VCCIO4 GNDIO4 PB7E PB8A PB8B PB8C PB8D PB8E PB8F VCCIO4 GNDIO4 PB9A PB9B PB9C PB9D PB9E PB9F PB10A PB10B GND PB10C PB10D NC PB10F PB11A PB11B PB11C PB11D VCCIO4 GNDIO4 GNDIO3 VCCIO3 PR16B PR16A PR15B PR15A PR14D PR14C PR14B PR14A PR13D PR13C PR13B VCCIO3 GNDIO3 PR13A PR12D PR12C PR12B PR12A PR11D PR11C PR11B 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 T** C T C** T** C T C** C T C** T** C T C** T** C T C** T C T C T C T C T C T C T C T T C T C T C
LAMXO2280 Ball Ball Differential Number Function Bank
VCCIO4 GND M10 R9 R10 T10 T11 N10 N11 VCCIO4 GND R11 R12 P11 P12 T13 T12 R13 R14 GND T14 T15 P13 P14 R15 R16 P15 P16 VCCIO4 GND GND VCCIO3 M11 L11 N12 N13 M13 M12 N14 N15 L13 L12 M14 VCCIO3 GND L14 N16 M16 M15 L15 L16 K16 K13 VCCIO4 GNDIO4 PB10A PB11C PB11D PB12A PB12B PB12C PB12D VCCIO4 GNDIO4 PB13A PB13B PB13C PB13D PB14A PB14B PB14C PB14D GND PB15A PB15B NC PB15D PB16A PB16B PB16C PB16D VCCIO4 GNDIO4 GNDIO3 VCCIO3 PR20B PR20A PR18B PR18A PR17D PR17C PR17B PR17A PR16D PR16C PR16B VCCIO3 GNDIO3 PR16A PR15D PR15C PR15B PR15A PR14D PR14C PR14B 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 T** C T C** T** C T C** C T C** T** C T C** T** C T C** T C T C T C T C T C T C T C T T C T C T C
Dual Function
Dual Function
Dual Function
Differential
4-16
Lattice Semiconductor
Pinout Information LA-MachXO Automotive Family Data Sheet
LA-MachXO640, LA-MachXO1200 and LA-MachXO2280 Logic Signal www..com Connections: 256 ftBGA (Cont.)
LAMXO640 Ball Ball Number Function Bank
J13 GND K14 J14 K15 J15 K12 J12 J16 H16 H15 G15 H14 G14 GND VCCIO1 H13 H12 G13 G12 G16 F16 F15 E15 E16 D16 VCCIO1 GND D15 C15 C16 B16 F14 E14 F12 F13 E12 E13 D13 D14 VCCIO0 GND GND VCCIO0 B15 A15 C14 B14 C13 B13 PR8C GND PR8B PR8A PR7D PR7C NC NC PR7B PR7A PR6B PR6A PR5D PR5C GNDIO1 VCCIO1 PR6D PR6C PR4D PR4C PR5B PR5A PR4B PR4A PR3B PR3A VCCIO1 GNDIO1 PR2D PR2C PR2B PR2A PR3D PR3C NC NC NC NC NC NC VCCIO0 GNDIO0 GNDIO0 VCCIO0 NC NC NC NC PT9F PT9E 0 0 C T 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C T C T C T C T C T C T C T C T C T C T C T 1 1 1 1 1 C T C T
LAMXO1200 Ball Ball Differential Number Function Bank
T J13 GND K14 J14 K15 J15 GND VCCIO3 K12 J12 J16 H16 H15 G15 H14 G14 GND VCCIO2 H13 H12 G13 G12 G16 F16 F15 E15 E16 D16 VCCIO2 GND D15 C15 C16 B16 F14 E14 F12 F13 E12 E13 D13 D14 VCCIO2 GND GND VCCIO1 B15 A15 C14 B14 C13 B13 PR11A GND PR10D PR10C PR10B PR10A GNDIO3 VCCIO3 PR9D PR9C PR9B PR9A PR8D PR8C PR8B PR8A GNDIO2 VCCIO2 PR7D PR7C PR7B PR7A PR6D PR6C PR6B PR6A PR5D PR5C VCCIO2 GNDIO2 PR5B PR5A PR4D PR4C PR4B PR4A PR3D PR3C PR3B PR3A PR2B PR2A VCCIO2 GNDIO2 GNDIO1 VCCIO1 PT11D PT11C PT11B PT11A PT10F PT10E 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 C T C T C T C T C** T** C T C** T** C T C** T** C T C** T** C T C** T** C T C T C** T** C T C** T** C T C** T**
LAMXO2280 Ball Ball Differential Number Function Bank
T** J13 GND K14 J14 K15 J15 GND VCCIO3 K12 J12 J16 H16 H15 G15 H14 G14 GND VCCIO2 H13 H12 G13 G12 G16 F16 F15 E15 E16 D16 VCCIO2 GND D15 C15 C16 B16 F14 E14 GND F12 F13 E12 E13 D13 D14 VCCIO2 GND GND VCCIO1 B15 A15 C14 B14 C13 B13 PR14A GND PR13D PR13C PR13B PR13A GNDIO3 VCCIO3 PR11D PR11C PR11B PR11A PR10D PR10C PR10B PR10A GNDIO2 VCCIO2 PR9D PR9C PR9B PR9A PR7D PR7C PR7B PR7A PR6D PR6C VCCIO2 GNDIO2 PR6B PR6A PR5D PR5C PR5B PR5A GND PR4D PR4C PR4B PR4A PR3B PR3A VCCIO2 GNDIO2 GNDIO1 VCCIO1 PT16D PT16C PT16B PT16A PT15D PT15C 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 C T C T C T C T C** T** C** T** C** T** C T C** T** C T C** T** C T C** T** C T C T C** T** C T C** T** C T C** T**
Dual Function
Dual Function
Dual Function
Differential
T**
4-17
Lattice Semiconductor
Pinout Information LA-MachXO Automotive Family Data Sheet
LA-MachXO640, LA-MachXO1200 and LA-MachXO2280 Logic Signal www..com Connections: 256 ftBGA (Cont.)
LAMXO640 Ball Ball Number Function Bank
E11 E10 D12 D11 A14 A13 C12 C11 B12 B11 A12 A11 GND B10 B9 D10 D9 C10 C9 A9 A10 E9 E8 D7 D8 VCCIO0 GND C8 B8 A8 A7 A6 B7 B6 C6 C7 A5 A4 E7 E6 B5 B4 D5 D6 C4 C5 D4 D3 NC NC PT9D PT9C PT7F PT7E PT8B PT8A PT7B PT7A PT7D PT7C GND PT5D PT5C PT8D PT8C PT6D PT6C PT6B PT6A PT9B PT9A PT5B PT5A VCCIO0 GNDIO0 PT4F PT4E VCCAUX PT4D PT4C PT4B PT4A PT3C PT3D PT3E PT3F NC NC PT3B PT3A PT2D PT2C PT2E PT2F NC NC 0 0 0 0 0 0 C T C T T C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C T C T T C T C C T PCLK0_0**** PCLK0_1**** C T C T C T C T 0 0 0 0 0 0 0 0 C T C T C T C T 0 0 0 0 0 0 C T C T C T
LAMXO1200 Ball Ball Differential Number Function Bank
E11 E10 D12 D11 A14 A13 C12 C11 VCCIO1 GND B12 B11 A12 A11 GND B10 B9 D10 D9 VCCIO1 GND C10 C9 A9 A10 E9 E8 D7 D8 VCCIO0 GND C8 B8 A8 A7 A6 B7 B6 C6 C7 A5 A4 E7 E6 B5 B4 D5 D6 C4 C5 D4 D3 PT10D PT10C PT10B PT10A PT9F PT9E PT9D PT9C VCCIO1 GNDIO1 PT9B PT9A PT8F PT8E GND PT8D PT8C PT8B PT8A VCCIO1 GNDIO1 PT7F PT7E PT7D PT7C PT7B PT7A PT6F PT6E VCCIO0 GNDIO0 PT6D PT6C VCCAUX PT6B PT6A PT5F PT5E PT5C PT5D PT5A PT5B PT4C PT4D PT3F PT3E PT3D PT3C PT4A PT4B PT2D PT2C 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C T C T C T T C T C T C C T C T T C C T PCLK1_0**** PCLK1_1**** C T C T C T C T C T C T C T C T
LAMXO2280 Ball Ball Differential Number Function Bank
C T C T C T C T E11 E10 D12 D11 A14 A13 C12 C11 VCCIO1 GND B12 B11 A12 A11 GND B10 B9 D10 D9 VCCIO1 GND C10 C9 A9 A10 E9 E8 D7 D8 VCCIO0 GND C8 B8 A8 A7 A6 B7 B6 C6 C7 A5 A4 E7 E6 B5 B4 D5 D6 C4 C5 GND D4 D3 PT15B PT15A PT14D PT14C PT14B PT14A PT13D PT13C VCCIO1 GNDIO1 PT12D PT12C PT12B PT12A GND PT11B PT11A PT10F PT10E VCCIO1 GNDIO1 PT10D PT10C PT10B PT10A PT9D PT9C PT9B PT9A VCCIO0 GNDIO0 PT8D PT8C VCCAUX PT7D PT7C PT7B PT7A PT6A PT6B PT6C PT6D PT6E PT6F PT5D PT5C PT5B PT5A PT4A PT4B GND PT3D PT3C 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C T C T C T T C T C T C C T C T T C C T PCLK1_0**** PCLK1_1**** C T C T C T C T C T C T C T C T
Dual Function
Dual Function
Dual Function
Differential
C T C T C T C T
4-18
Lattice Semiconductor
Pinout Information LA-MachXO Automotive Family Data Sheet
LA-MachXO640, LA-MachXO1200 and LA-MachXO2280 Logic Signal www..com Connections: 256 ftBGA (Cont.)
LAMXO640 Ball Ball Number Function Bank
A3 A2 B3 B2 VCCIO0 GND A1 A16 F11 G8 G9 H7 H8 H9 H10 J7 J8 J9 J10 K8 K9 L6 T1 T16 G7 G10 K7 K10 H6 G6 K6 J6 L8 L7 L9 L10 K11 J11 H11 G11 F9 F10 F8 F7 PT2B PT2A NC NC VCCIO0 GNDIO0 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO0 VCCIO0 VCCIO0 VCCIO0 0 0 3 3 3 3 2 2 2 2 1 1 1 1 0 0 0 0 0 0
LAMXO1200 Ball Ball Differential Number Function Bank
C T A3 A2 B3 B2 VCCIO0 GND A1 A16 F11 G8 G9 H7 H8 H9 H10 J7 J8 J9 J10 K8 K9 L6 T1 T16 G7 G10 K7 K10 H6 G6 K6 J6 L8 L7 L9 L10 K11 J11 H11 G11 F9 F10 F8 F7 PT3B PT3A PT2B PT2A VCCIO0 GNDIO0 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCCIO7 VCCIO7 VCCIO6 VCCIO6 VCCIO5 VCCIO5 VCCIO4 VCCIO4 VCCIO3 VCCIO3 VCCIO2 VCCIO2 VCCIO1 VCCIO1 VCCIO0 VCCIO0 0 0 0 0 0 0 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0
LAMXO2280 Ball Ball Differential Number Function Bank
C T C T A3 A2 B3 B2 VCCIO0 GND A1 A16 F11 G8 G9 H7 H8 H9 H10 J7 J8 J9 J10 K8 K9 L6 T1 T16 G7 G10 K7 K10 H6 G6 K6 J6 L8 L7 L9 L10 K11 J11 H11 G11 F9 F10 F8 F7 PT3B PT3A PT2D PT2C VCCIO0 GNDIO0 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCCIO7 VCCIO7 VCCIO6 VCCIO6 VCCIO5 VCCIO5 VCCIO4 VCCIO4 VCCIO3 VCCIO3 VCCIO2 VCCIO2 VCCIO1 VCCIO1 VCCIO0 VCCIO0 0 0 0 0 0 0 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0
Dual Function
Dual Function
Dual Function
Differential
C T C T
* LCMXO640 only. ** Supports true LVDS outputs. *** NC for "E" devices. **** Primary clock inputs are single-ended.
4-19
Lattice Semiconductor
Pinout Information LA-MachXO Automotive Family Data Sheet
www..com LA-MachXO2280 Logic Signal Connections: 324 ftBGA
LAMXO2280 Ball Number GND VCCIO7 D4 F5 B3 C3 E4 G6 A1 B1 F4 VCC E3 D2 D3 G5 F3 C2 VCCIO7 GND C1 H5 G4 E2 D1 J6 H4 F2 E1 GND J3 J5 G3 H3 K3 K5 F1 VCCIO7 GND G1 K4 K6 Ball Function GNDIO7 VCCIO7 PL2A PL2B PL3A PL3B PL3C PL3D PL4A PL4B PL4C VCC PL4D PL5A PL5B PL5C PL5D PL6A VCCIO7 GNDIO7 PL6B PL6C PL6D PL7A PL7B PL7C PL7D PL8A PL8B GND PL8C PL8D PL9A PL9B PL9C PL9D PL10A VCCIO7 GNDIO7 PL10B PL10C PL10D Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 C* T C T C T* C* T C T* GSRN C* T C T* C* T C T* C* C T* C* T C T* LUM0_PLLT_IN_A LUM0_PLLC_IN_A LUM0_PLLT_FB_A LUM0_PLLC_FB_A T C T* C* T C T* C* T Dual Function Differential
4-20
Lattice Semiconductor
Pinout Information LA-MachXO Automotive Family Data Sheet
LA-MachXO2280 Logic Signal Connections: 324 ftBGA (Cont.) www..com
LAMXO2280 Ball Number G2 H2 L3 L5 H1 VCCIO6 GND J2 L4 L6 K2 K1 J1 VCC L2 M5 M3 L1 M2 M1 N1 M6 M4 VCCIO6 GND P1 P2 N3 N4 GND T1 R1 P3 N5 R3 R2 P4 N6 U1 VCCIO6 GND GND VCCIO5 Ball Function PL11A PL11B PL11C PL11D PL12A VCCIO6 GNDIO6 PL12B PL12C PL12D PL13A PL13B PL13C VCC PL13D PL14D PL14C PL14B PL14A PL15A PL15B PL15C PL15D VCCIO6 GNDIO6 PL16A PL16B PL16C PL16D GND PL17A PL17B PL17C PL17D PL18A PL18B PL19A PL19B PL20A VCCIO6 GNDIO6 GNDIO5 VCCIO5 Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 LLM0_PLLT_IN_A LLM0_PLLC_IN_A LLM0_PLLT_FB_A LLM0_PLLC_FB_A T* C* T C T* C* T C T T* C* T C TSALL C C T C* T* T* C* T C C* T C T* C* T Dual Function Differential T* C* T C T*
4-21
Lattice Semiconductor
Pinout Information LA-MachXO Automotive Family Data Sheet
LA-MachXO2280 Logic Signal Connections: 324 ftBGA (Cont.) www..com
LAMXO2280 Ball Number T2 P6 V1 U2 T3 N7 R4 R5 T4 VCC R6 P7 U3 T5 V2 N8 V3 T6 GND VCCIO5 U4 P8 T7 V4 R8 N9 U5 V5 U6 VCC V6 P9 T8 U7 V7 M10 U8 V8 VCCIO5 GND T9 U9 V9 Ball Function PL20B TMS PB2A PB2B PB2C TCK PB2D PB3A PB3B VCC PB3C PB3D PB4A PB4B PB4C TDO PB4D PB5A GNDIO5 VCCIO5 PB5B PB5C PB5D TDI PB6A PB6B PB6C PB6D PB7A VCC PB7B PB7C PB7D PB8A PB8B VCCAUX PB8C PB8D VCCIO5 GNDIO5 PB8E PB8F PB9A Bank 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 T C T T C C T C T C TDI T C T C T C T C TDO C T T C T C T TCK C T C TMS T C T Dual Function Differential C
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Lattice Semiconductor
Pinout Information LA-MachXO Automotive Family Data Sheet
LA-MachXO2280 Logic Signal Connections: 324 ftBGA (Cont.) www..com
LAMXO2280 Ball Number V10 N10 R10 P10 T10 U10 V11 U11 VCCIO4 GND T11 U12 R11 GND T12 P11 V12 V13 R12 N11 U13 VCCIO4 GND V14 T13 P12 R13 N12 V15 U14 V16 GND T14 U15 V17 P13 T15 U16 V18 N13 R14 VCCIO4 GND Ball Function PB9B PB9C PB9D PB10F PB10E PB10D PB10C PB10B VCCIO4 GNDIO4 PB10A PB11A PB11B GND PB11C PB11D PB12A PB12B PB12C PB12D PB12E VCCIO4 GNDIO4 PB12F PB13A PB13B PB13C PB13D PB14A PB14B PB14C GND PB14D PB15A PB15B NC PB15D PB16A PB16B PB16C PB16D VCCIO4 GNDIO4 Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 T C T C C T C C T C T C T C T T C T C T C T T T C PCLK4_0** PCLK4_1** Dual Function Differential C T C C T C T C
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Lattice Semiconductor
Pinout Information LA-MachXO Automotive Family Data Sheet
LA-MachXO2280 Logic Signal Connections: 324 ftBGA (Cont.) www..com
LAMXO2280 Ball Number GND VCCIO3 P15 N14 N15 M13 R15 T16 N16 M14 U17 VCC U18 R17 R16 P16 VCCIO3 GND P17 L13 M15 T17 T18 L14 L15 R18 P18 GND K15 K13 N17 N18 K16 K14 M16 L16 GND VCCIO3 J16 J14 M17 L17 J15 Ball Function GNDIO3 VCCIO3 PR20B PR20A PR19B PR19A PR18B PR18A PR17D PR17C PR17B VCC PR17A PR16D PR16C PR16B VCCIO3 GNDIO3 PR16A PR15D PR15C PR15B PR15A PR14D PR14C PR14B PR14A GND PR13D PR13C PR13B PR13A PR12D PR12C PR12B PR12A GNDIO3 VCCIO3 PR11D PR11C PR11B PR11A PR10D Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 C T C* T* C C T C* T* C T C* T* T* C T C* T* C T C* T* T* C T C* C T C T C* T* C T C* Dual Function Differential
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Lattice Semiconductor
Pinout Information LA-MachXO Automotive Family Data Sheet
LA-MachXO2280 Logic Signal Connections: 324 ftBGA (Cont.) www..com
LAMXO2280 Ball Number J13 M18 L18 GND VCCIO2 H16 H14 K18 J18 J17 VCC H18 H17 G17 H13 H15 G18 F18 G14 G16 VCCIO2 GND E18 F17 G13 G15 E17 E16 GND F15 E15 D17 D18 B18 C18 C16 D16 C17 D15 VCCIO2 GND GND VCCIO1 Ball Function PR10C PR10B PR10A GNDIO2 VCCIO2 PR9D PR9C PR9B PR9A PR8D VCC PR8C PR8B PR8A PR7D PR7C PR7B PR7A PR6D PR6C VCCIO2 GNDIO2 PR6B PR6A PR5D PR5C PR5B PR5A GND PR4D PR4C PR4B PR4A PR3D PR3C PR3B PR3A PR2B PR2A VCCIO2 GNDIO2 GNDIO1 VCCIO1 Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 C T C* T* C T C* T* C T C* T* C T C* T* T C* T* C T C* T* C T C T C* T* C Dual Function Differential T C* T*
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Lattice Semiconductor
Pinout Information LA-MachXO Automotive Family Data Sheet
LA-MachXO2280 Logic Signal Connections: 324 ftBGA (Cont.) www..com
LAMXO2280 Ball Number E13 C15 F13 D14 A18 B17 A16 A17 VCC D13 F12 C14 E12 C13 B16 B15 A15 VCCIO1 GND B14 A14 D12 F11 B13 A13 C12 GND B12 E11 D11 C11 A12 VCCIO1 GND F10 D10 B11 A11 E10 C10 D9 E9 B10 Ball Function PT16D PT16C PT16B PT16A PT15D PT15C PT15B PT15A VCC PT14D PT14C PT14B PT14A PT13D PT13C PT13B PT13A VCCIO1 GNDIO1 PT12F PT12E PT12D PT12C PT12B PT12A PT11D GND PT11C PT11B PT11A PT10F PT10E VCCIO1 GNDIO1 PT10D PT10C PT10B PT10A PT9D PT9C PT9B PT9A PT8F Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 PCLK1_0*** PCLK1_1*** C T C T C T C T C T C T C T C T C T C T C C T C T C T C T Dual Function Differential C T C T C T C T
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Lattice Semiconductor
Pinout Information LA-MachXO Automotive Family Data Sheet
LA-MachXO2280 Logic Signal Connections: 324 ftBGA (Cont.) www..com
LAMXO2280 Ball Number A10 VCCIO0 GND A9 C9 B9 F9 A8 B8 C8 VCC A7 B7 A6 B6 D8 F8 C7 E8 D7 VCCIO0 GND E7 A5 C6 B5 A4 D6 F7 B4 GND C5 F6 E5 E6 D5 A3 C4 A2 B2 VCCIO0 GND E14 Ball Function PT8E VCCIO0 GNDIO0 PT8D PT8C PT8B VCCAUX PT8A PT7D PT7C VCC PT7B PT7A PT6A PT6B PT6C PT6D PT6E PT6F PT5D VCCIO0 GNDIO0 PT5C PT5B PT5A PT4A PT4B PT4C PT4D PT4E GND PT4F PT3D PT3C PT3B PT3A PT2D PT2C PT2B PT2A VCCIO0 GNDIO0 GND Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C C T C T C T C T T C T T C T C T C T T C T C T C C T C T C T C Dual Function Differential T
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Lattice Semiconductor
Pinout Information LA-MachXO Automotive Family Data Sheet
LA-MachXO2280 Logic Signal Connections: 324 ftBGA (Cont.) www..com
LAMXO2280 Ball Number F16 H10 H11 H8 H9 J10 J11 J4 J8 J9 K10 K11 K17 K8 K9 L10 L11 L8 L9 N2 P14 P5 R7 F14 G11 G9 H7 L7 M9 H6 J7 M7 K7 M8 R9 M12 M11 L12 K12 J12 H12 G12 G10 Ball Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCCIO7 VCCIO7 VCCIO6 VCCIO6 VCCIO5 VCCIO5 VCCIO4 VCCIO4 VCCIO3 VCCIO3 VCCIO2 VCCIO2 VCCIO1 VCCIO1 Bank 7 7 6 6 5 5 4 4 3 3 2 2 1 1 Dual Function Differential
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Lattice Semiconductor
Pinout Information LA-MachXO Automotive Family Data Sheet
LA-MachXO2280 Logic Signal Connections: 324 ftBGA (Cont.) www..com
LAMXO2280 Ball Number G8 G7 Ball Function VCCIO0 VCCIO0 Bank 0 0 Dual Function Differential
* Supports true LVDS outputs. ** Primary clock inputs are single-ended.
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Lattice Semiconductor
Pinout Information LA-MachXO Automotive Family Data Sheet
Thermal Management www..com
Thermal management is recommended as part of any sound FPGA design methodology. To assess the thermal characteristics of a system, Lattice specifies a maximum allowable junction temperature in all device data sheets. Designers must complete a thermal analysis of their specific design to ensure that the device and package do not exceed the junction temperature limits. Refer to the Thermal Management document to find the device/package specific thermal values.
For Further Information
For further information regarding Thermal Management, refer to the following located on the Lattice website at www.latticesemi.com. * Thermal Management document * Technical Note TN1090 - Power Estimation and Management for MachXO Devices * Power Calculator tool included with Lattice's ispLEVER design tool, or as a standalone download from www.latticesemi.com/software
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www..com
LA-MachXO Automotive Family Data Sheet Ordering Information
Data Sheet DS1003
April 2006
Part Number Description
LAMXO XXXX X - X XXXXXX X
Device Family LA-MachXO Automotive Crossover PLD Logic Capacity 256 LUTs = 256 640 LUTs = 640 1200 LUTs = 1200 2280 LUTs = 2280 Supply Voltage C = 1.8V/2.5V/3.3V E = 1.2V
Note: Parts dual marked as described.
Grade E = Automotive Package TN100 = 100-pin Lead-Free TQFP TN144 = 144-pin Lead-Free TQFP FTN256 = 256-ball Lead-Free ftBGA FTN324 = 324-ball Lead-Free ftBGA Speed 3 = -3 Speed Grade
Ordering Information
Part Number LAMXO256C-3TN100E LAMXO640C-3TN100E LAMXO640C-3TN144E LAMXO640C-3FTN256E LAMXO256E-3TN100E LAMXO640E-3TN100E LAMXO640E-3TN144E LAMXO640E-3FTN256E LAMXO1200E-3TN100E LAMXO1200E-3TN144E LAMXO1200E-3FTN256E LAMXO2280E-3TN100E LAMXO2280E-3TN144E LAMXO2280E-3FTN256E LAMXO2280E-3FTN324E LUTs 256 640 640 640 256 640 640 640 1200 1200 1200 2280 2280 2280 2280 Supply Voltage 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.8V/2.5V/3.3V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V I/Os 78 74 113 159 78 74 113 159 73 113 211 73 113 211 271 Grade -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 -3 Package Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free ftBGA Lead-Free TQFP Lead-Free TQFP Lead-Free TQFP Lead-Free ftBGA Lead-Free TQFP Lead-Free TQFP Lead-Free ftBGA Lead-Free TQFP Lead-Free TQFP Lead-Free ftBGA Lead-Free ftBGA Pins 100 100 144 256 100 100 144 256 100 144 256 100 144 256 324 Temp. AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO AUTO
(c) 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
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DS1003 Ordering Information_01.0
www..com
LA-MachXO Automotive Family Data Sheet Supplemental Information
Data Sheet DS1003
November 2007
For Further Information
A variety of technical notes for the LA-MachXO family are available on the Lattice web site at www.latticesemi.com. * * * * * * * * MachXO sysIO Usage Guide (TN1091) MachXO sysCLOCK PLL Design and Usage Guide (TN1089) MachXO Memory Usage Guide (TN1092) Power Estimation and Management for MachXO Devices (TN1090) MachXO JTAG Programming and Configuration User's Guide (TN1086) Minimizing System Interruption During Configuration Using TransFR Technology (TN1087) MachXO Density Migration (TN1097) IEEE 1149.1 Boundary Scan Testability in Lattice Devices
For further information on interface standards refer to the following web sites: * JEDEC Standards (LVTTL, LVCMOS): www.jedec.org * PCI: www.pcisig.com
(c) 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
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DS1003 Further Information_01.1
www..com
LA-MachXO Automotive Family Data Sheet Revision History
Data Sheet DS1003
November 2007
Revision History
Date April 2006 May 2006 Version 01.0 01.1 Section -- Pinout Information Initial release. Removed [LOC][0]_PLL_RST from Signal Descriptions table. PCLK footnote added to appropriate pins in Logic Signal Connections tables. November 2006 01.2 DC and Switching Characteristics Corrections to MachXO "C" Sleep Mode Timing table - value for tWSLEEPN (400ns) changed from max. to min. Value for tWAWAKE (100ns) changed from min. to max. Added Flash Download Time table. December 2006 February 2007 November 2007 01.3 01.4 01.5 Architecture Pinout Information Architecture DC and Switching Characteristics Pinout Information Supplemental Information EBR Asynchronous Reset section added. Power Supply and NC table: Pin/Ball orientation footnotes added. Updated EBR Asynchronous Reset section. Updated sysIO Single-Ended DC Electrical Characteristics table. Added JTAG Port Timing Waveforms diagram. Added Thermal Management text section. Updated title list. Change Summary
(c) 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
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